Computer Discussion: Why Integer Division Is Not Available In SSE?Group: comp.arch Discussion: Why Integer Division Is Not Available In SSE? Add this discussion to your Favorites Posts: 11
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Michael S 
Dec 28, 2010  11:45:53 am EST 
On Dec 28, 2:42=A0pm, n... [No Spam] cam.ac.uk wrote:
> In article ,
>
>
> It's a little LESS complex than floatingpoint.
For a given register size (i.e. 32b or 64b) I'd expect floating point
division to be slightly more complex than integer division but also,
due to fewer significant bits, more than slightly faster.
Now, taking into account that when you build integer division unit you
likely want that the same unit will be capable to produce reminders, I
am not even sure that it will end up less complex.

MitchAlsup 
Dec 28, 2010  09:54:35 pm EST 
On Dec 28, 6:39=A0am, jogging wrote:
> Hi, all
>
> Recently I have such a situation:
> there is integer division operation in my program.
> I intend to use SSE intrinsics to rewrite that part of
> the program. I haven't used integer division instructions
> before. From instruction manual, I find that such
> instructions are not available.
> But SSEs for floating point division is available.
> I guess integer division is used less compared to
> integer multiplication, so it is not necessary to
> put such complex logic into the chip.
> Is the logic for integer division very complex?
>
> Best Regards
> Jogging
Integer division has several unuseful properties that make it harder
to include in the short vector formal of SSE.
Many good integer divide algorithms are cyclecount dependent on the
operands, short vectors disallow these implementations.
Most of the algorithms for which MMX (firstly then SSE later) were
designed for either don't need division (FIR,...) or can approximate
division with a multiplication.
Then If the SSE architecture added integer division, it would only
change the complaint space into "why can't we now have integer modulo/
remainder". And no reasonable architect would want to put that in SSE.
Actually computing the bits is easy. The logic already exists and
could be easily cut and pasted. It would burn some power, add
complexity to the SSE/MMX pipeline; but the manufactures would not get
a single penny for its inclusion.
Mtich

Andy \Krazy\ Glew <arch.net> 
Jan 01, 2011  08:25:27 pm EST 
On 12/28/2010 6:54 PM, MitchAlsup wrote:
> On Dec 28, 6:39 am, jogging wrote:
>> Hi, all
>>
>> Recently I have such a situation:
>> there is integer division operation in my program.
>> I intend to use SSE intrinsics to rewrite that part of
>> the program. I haven't used integer division instructions
>> before. From instruction manual, I find that such
>> instructions are not available.
>> But SSEs for floating point division is available.
>> I guess integer division is used less compared to
>> integer multiplication, so it is not necessary to
>> put such complex logic into the chip.
>> Is the logic for integer division very complex?
>>
>> Best Regards
>> Jogging
>
> Integer division has several unuseful properties that make it harder
> to include in the short vector formal of SSE.
>
> Many good integer divide algorithms are cyclecount dependent on the
> operands, short vectors disallow these implementations.
> Most of the algorithms for which MMX (firstly then SSE later) were
> designed for either don't need division (FIR,...) or can approximate
> division with a multiplication.
>
> Then If the SSE architecture added integer division, it would only
> change the complaint space into "why can't we now have integer modulo/
> remainder". And no reasonable architect would want to put that in SSE.
I guess that I am an unreasonable computer architect.
The question is really just "Who needs it?" What workloads can benefit
from the ability to do SIMD packed vector integer divide, with modulus
and/or remainder? Signed/unsigned?
Who could use it? Crypto? If nobody important enough, do not waste the
opcode space and validation effort.
However, yesterday I posted (or should have posted, while traveling back
from Canada) where my head is at wrt the proliferation of instructions,
at least for a aggressive forward looking manner: multiple inputs,
multiple outputs, instruction set and opcode uncontrained by 16 or 32
bits, with the ability to map a subset into a small, 16b or 32b,
instruction set.


Jan 03, 2011  12:41:51 am EST 
On Jan 1, 7:25=A0pm, "Andy \"Krazy\" Glew"
wrote:
> On 12/28/2010 6:54 PM, MitchAlsup wrote:
> > Then If the SSE architecture added integer division, it would only
> > change the complaint space into "why can't we now have integer modulo/
> > remainder". And no reasonable architect would want to put that in SSE.
>
> I guess that I am an unreasonable computer architect.
>
> The question is really just "Who needs it?" =A0What workloads can benefit
> from the ability to do SIMD packed vector integer divide, with modulus
> and/or remainder? =A0Signed/unsigned?
>
> Who could use it? =A0Crypto? =A0If nobody important enough, do not waste =
the
> opcode space and validation effort.
Not crypto. All the numbers where division (or modulus) are
interesting are far too big, and everyone uses some variant of Newton–
Raphson. While improving the initial estimate is slightly helpful,
what that one really needs is fast bignum multiplication performance.

Noob 
Jan 03, 2011  04:15:23 am EST 
Nick Maclaren wrote:
> I like the idea of an arithmetic unit producing reminders :)
Most people just use sticky notes :?

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