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Adam S...
Posted: Wed Jul 09, 2008 10:45 pm
Guest
I'm making a 24 to 5V at (no spam) 12A DC-DC convert with accurate constant current
limiting down to zero volts. After spending time designing a prototype
using TI's UCC2541 synchronous buck controller, I discovered this IC has
as a serious problem at low duty cycles. When the PWM on period is
between 0 and 100ns the high-side FET fails to turn off correctly,
causing catastrophic shoot through currents across low-side and
high-side MOSFETs. I am now looking at different synchronous buck
controller ICs.

It seems that all available ICs specify some minimum PWM on period
(typically 50 to 150ns), thereby limiting the lowest controllable output
voltage. I don't mind the control loop going a little chaotic at extreme
low output voltage, but it must be capable of averaging out to a
constant current into a short circuit.

Anyone know what is meant by controller minimum on period ?
Does it mean:
1) Shortest on period regardless how low the programmed duty cycle.
2) Shortest on period while maintaining reliable control. Periods
shorter than this are considered uncontrollable due to noise.

None of the buck controller datasheets clearly state what happens.

Adam
Adam S...
Posted: Sat Jul 12, 2008 9:49 pm
Guest
legg wrote:
Quote:

A simple method of avoiding shoot-through here, is not to use the
synchronous rectifier. Replace the bottom fet with a schottky diode.

Synchronous rectification has it's place.
Predictive gate drive of a synchronous rectifier has its place.
Integrated comntrollers have their place.

What you probably need here is a simple buck regulator that will
cycle-skip below a certain duty cycle.

OV or zero current are both difficult ("undefined") conditions to
'regulate', unless there's a means to reduce or reverse stored energy
in the inductor during the free-wheeling period.

Synchronous rectification handles the zero-current condition nicely. A
minimum or switched internal load will serve otherwise. For zero
voltage, a nice freewheeling voltage loss comes in handy in the
absence of a negative supply, but cannot be counted on to actually
reverse energy flow in each cycle - so there's still a minimum current
under which zero output volts can be regulated. The lower the voltage,
the higher this current will be.

Cycle skipping will occur naturally in most (all?) single-quadrant
regulators around the "undefined" operating conditions. This is
naturally chaotic, but generally benign and is useful in stretching
out performance extremes. However it likely unsuited to any
'predictive' technique. Perhaps that is what is actually being seen
here.

RL


Thanks very much for your tips. Unfortunately, power dissipation
restrictions don't allow me to do away with synchronous rectification. I
am taking your suggestion of going a less integrated approach.
Looks like I can use a simple voltage mode PWM controller IC along with
a synchronous MOSFET driver IC.
My calculations show that I need under 50ns of dead time, to avoid
excessive synchronous rectifier diode conduction losses. I believe any
of the adaptive dead time controlled MOSFET drivers can easily achieve
this range, while still allowing ON times approaching zero.

Adam
 
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