| |
 |
|
|
Science Forum Index » Electronics - Design Forum » AS91L1003S10L100IF datasheet...
Page 1 of 1
|
| Author |
Message |
| ... |
 Posted: Wed Jun 25, 2008 4:10 pm |
|
|
|
Guest
|
Description
The AS91L1006BU is a one to 6-port JTAG gateway. It partitions a
single JTAG chain into six separate chains. These separate chains
can be optionally configured to operate as a single
chain. The AS91L1006BU device is used to provide enhanced
capabilities to the standard
IEEE1149.1. It enables the IEEE1149.1 interface to be used in a true
Multi-Drop environment without any additional signals. This Multi-Drop
capability enables the standard IEEE1149.1 interface to be used not
just for stand alone PCB (Printed Circuit Board) testing, but also for
complete system
testing including all PCBs within a system back plane environment. The
AS91L1006BU provides the capability of partitioning the PCB, into
multiple smaller IEEE1149.1 scan chains totally under software
control. Partitioning the IEEE1149.1 chains on the PCB has several
benefits which include easier fault diagnostics capabilities as a
fault on one of the IEEE1149.1 Local Scan Ports (LSPs) does not
render the PCB untestable, faster flash programming on the PCBs, and
removal of IEEE1149.1 signal loading issues. All of the protocols
required for addressing the AS91L1006BU device via the Multi-Drop
capability and the protocols for configuring which of the six
IEEE1149.1 LSPs on the AS91L1006BU are to be used, is handled viard 3
party ATPG tools from vendors like Asset-Intertech and JTAG
Technologies. In a Multi-Drop environment it is also possible to
perform interconnect tests between multiple PCBs within a system thus
extending the interconnect tests to the back plane itself.
For AS91L1003S10L100IF datasheet and pdf download :http://
www.chinaicmart.com/series-AS9/AS91L1003S10L100IF.html |
|
|
| Back to top |
|
| |
|
Page 1 of 1
All times are GMT - 5 Hours
The time now is Fri Dec 05, 2008 9:33 am
|
|