I'm in the process of redesigning a RAM expansion board for an old Apple IIe series computer to help me better understand how
electronics work. Some of you may remember the Apple IIe from back in the 80's. I've found it's a great platform to learn on.
Anyway, the RAM expansion board uses 1 Meg x 1 bit DRAM's and I want to modify the board to use 1 Meg x 4 bit DRAM's. Just a
little homebrew project to further my knowledge of DRAM IC's and the circuits that drive them.

Here's the datasheet for the 1 Meg x 1 bit DRAM's: http://reactivecomputers.gotdns.com/Data%20Sheets/1Meg%20x%201bit%20DRAM.pdf

Here's the datasheet for the 1 Meg x 4 bit DRAM's: http://reactivecomputers.gotdns.com/Data%20Sheets/1Meg%20x%204bit%20DRAM.pdf

I'm in the process of redesigning a RAM expansion board for an old Apple
IIe series computer to help me better understand how electronics work.
Some of you may remember the Apple IIe from back in the 80's. I've found
it's a great platform to learn on. Anyway, the RAM expansion board uses 1
Meg x 1 bit DRAM's and I want to modify the board to use 1 Meg x 4 bit
DRAM's. Just a little homebrew project to further my knowledge of DRAM
IC's and the circuits that drive them.

Here's the datasheet for the 1 Meg x 1 bit DRAM's:
http://reactivecomputers.gotdns.com/Data%20Sheets/1Meg%20x%201bit%20DRAM.pdf

Here's the datasheet for the 1 Meg x 4 bit DRAM's:
http://reactivecomputers.gotdns.com/Data%20Sheets/1Meg%20x%204bit%20DRAM.pdf


A friend of mine has been helping me a bit along the way too. After we
studied the two data sheets we noticed that the 4 bit DRAM has an Output
Enable pin which the 1 bit DRAM does not. It would seen to me that if I
invert the Write signal with a 74LS05 then I could use it to drive the
Output Enable pin. So I wired the 74LS05 in to the circuit . I then
wired up the rest of the signals accordingly. I took IO1 and connected it
to where the first 1 bit DRAM I/O would be, IO2 and connected it to where
the second 1 bit DRAM I/O would be, and so on. On my board the 1 bit
DRAM's have pin 1 and 17 wired together. I then have the four remaining
sockets in the bank of eight DRAM's filled with 1 bit DRAM IC's.

Next I insert my board in to the computer, run my RAM test and... it
fails. The program tests each DRAM separately, so the 1 bit DRAM's pass
the test but the 4 bit DRAM fails. I've even tried several different
brands of 4 bit DRAM's too. I can't seem to see a reason why it would
fail, at least not according to the data sheets.

Does anyone have any experience with what I'm doing or maybe can see
something I'm missing from the data sheets? As you can probably guess I'm
a little stumped and have been trying all sort of things for the past
couple weeks. Any help would or guidance would be appreciated.



Henry

Hey guys. Thanks for the reply.

petrus bitbyter: I did compare the waveforms of the datasheets and they do match up, or I should say they match to my eye. The
board I'm working with is actually an expansion board to another card. I guess I'll have to draw the schematic to the main card
to really understand how and what the main card is doing and what it expects from the daughter board. Thanks for the advice!


Helmut Sennewald: Concerning the refresh cycles - If I'm looking in the right place on the data sheets I see the 1bit DRAM
requires 512 cycles every 8 ms and the 4bit DRAM requires 1024 cycles every 16 ms. Isn't this the same thing or am I confusing
something? Thanks.


Henry

The best solution is to find a 1M*4 DRAM with 512 refresh cycles.
The type with 1024 refresh cycles can't be used if you haven't
the possibility to increase the refresh to 1024 cycles.

Hey guys. Thanks for the reply.

petrus bitbyter: I did compare the waveforms of the datasheets and they
do match up, or I should say they match to my eye. The board I'm
working with is actually an expansion board to another card. I guess
I'll have to draw the schematic to the main card to really understand
how and what the main card is doing and what it expects from the
daughter board. Thanks for the advice!


Helmut Sennewald: Concerning the refresh cycles - If I'm looking in the
right place on the data sheets I see the 1bit DRAM requires 512 cycles
every 8 ms and the 4bit DRAM requires 1024 cycles every 16 ms. Isn't
this the same thing or am I confusing something? Thanks.
The problem is that two lots of 512 cycles, do not activate the extra