On Sun, 06 Jul 2008 12:27:26 -0700, Tim Wescott <t... at (no spam) seemywebsite.com
wrote:



Jim Thompson wrote:
On Sun, 06 Jul 2008 11:42:09 -0700, John Larkin
jjlar... at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 06 Jul 2008 11:28:23 -0700, Jim Thompson
To-Email-Use-The-Envelope-I... at (no spam) My-Web-Site.com> wrote:

-- snip --

Pico-second speeds in CMOS are power hogs... my usual design
cross-over point is around 250-300MHz.

In a WiFi repeater chip I come from 5GHz down to 250MHz in CML, then
CMOS.

                                        ...Jim Thompson

Yes, but you went to school back when "circuit design" meant "circuit
design", not "simulating things you don't understand on software you
don't understand using a process you don't understand."

Yep.  I was educated 1958-1962 BC (before computers
                                                       |

On Sun, 6 Jul 2008 19:34:54 -0700 (PDT), bill.slo... at (no spam) ieee.org wrote:
On Jul 7, 5:39 am, Jim Thompson <To-Email-Use-The-Envelope-I... at (no spam) My-Web-
Site.com> wrote:
On Sun, 06 Jul 2008 12:27:26 -0700, Tim Wescott <t... at (no spam) seemywebsite.com
wrote:

Jim Thompson wrote:
On Sun, 06 Jul 2008 11:42:09 -0700, John Larkin
jjlar... at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 06 Jul 2008 11:28:23 -0700, Jim Thompson
To-Email-Use-The-Envelope-I... at (no spam) My-Web-Site.com> wrote:

-- snip --

Pico-second speeds in CMOS are power hogs... my usual design
cross-over point is around 250-300MHz.

In a WiFi repeater chip I come from 5GHz down to 250MHz in CML, then
CMOS.

                                        ...Jim Thompson

Yes, but you went to school back when "circuit design" meant "circuit
design", not "simulating things you don't understand on software you
don't understand using a process you don't understand."

Yep.  I was educated 1958-1962 BC (before computers
                                                       |
Must have been a crap university - the University of Melbourne in
Australia had a computer on-site from 1956

http://en.wikipedia.org/wiki/CSIRAC

I suppose that, for some people, being offensive is more important
than being right.

http://www.cedmagic.com/history/whirlwind-computer.html

http://en.wikipedia.org/wiki/Whirlwind_(computer)

On Sun, 06 Jul 2008 11:42:09 -0700, John Larkin
jjlarkin at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 06 Jul 2008 11:28:23 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon at (no spam) My-Web-Site.com> wrote:


On Sun, 06 Jul 2008 10:35:07 -0700, John Larkin
jjlarkin at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

[snip]

One problem with running CMOS at high speeds is power consumption.
They don't mention this in any usable form.

Fabless...

Potato Semiconductor Corporation is a private fabless IC design house
which locates in San Jose, California.

In and Out via CMOS, probably CML or PECL inside...

Why ecl inside? CMOS logic can already get down to sub-100 ps logic
functions "inside", as is common in fpga's and high-end processors.
The speed problem is i/o.



By applying our powerful industry-leading technology in IO interface,
logic cells & special design rule, we can design most of existing
chips with higher frequency, higher performance, higher reliability,
and less noise.

I've seen no patents assigned to Potato, or to their guru, Richard
Kao.



Their English is atrocious.

John



Taiwan

Design center is in San Jose. Fab is said to be by TSMC. They may be
real, but the specs are dicey.

John



Pico-second speeds in CMOS are power hogs... my usual design
cross-over point is around 250-300MHz.

In a WiFi repeater chip I come from 5GHz down to 250MHz in CML, then
CMOS.

...Jim Thompson

On Sun, 06 Jul 2008 12:16:03 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon at (no spam) My-Web-Site.com> wrote:


On Sun, 06 Jul 2008 11:42:09 -0700, John Larkin
jjlarkin at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 06 Jul 2008 11:28:23 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon at (no spam) My-Web-Site.com> wrote:


On Sun, 06 Jul 2008 10:35:07 -0700, John Larkin
jjlarkin at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

[snip]

One problem with running CMOS at high speeds is power consumption.
They don't mention this in any usable form.

Fabless...

Potato Semiconductor Corporation is a private fabless IC design house
which locates in San Jose, California.

In and Out via CMOS, probably CML or PECL inside...

Why ecl inside? CMOS logic can already get down to sub-100 ps logic
functions "inside", as is common in fpga's and high-end processors.
The speed problem is i/o.



By applying our powerful industry-leading technology in IO interface,
logic cells & special design rule, we can design most of existing
chips with higher frequency, higher performance, higher reliability,
and less noise.

I've seen no patents assigned to Potato, or to their guru, Richard
Kao.



Their English is atrocious.

John



Taiwan

Design center is in San Jose. Fab is said to be by TSMC. They may be
real, but the specs are dicey.

John



Pico-second speeds in CMOS are power hogs... my usual design
cross-over point is around 250-300MHz.

In a WiFi repeater chip I come from 5GHz down to 250MHz in CML, then
CMOS.

...Jim Thompson

FPGAs manage a million gates at 600 MHz or so. Some of the cmos LVDS
parts run at a couple of GHz. It deosn't seem like simple gates and
flops would be a power problem in cmos.

John

On Jul 7, 5:39 am, Jim Thompson <To-Email-Use-The-Envelope-I... at (no spam) My-Web-
Site.com> wrote:
On Sun, 06 Jul 2008 12:27:26 -0700, Tim Wescott <t... at (no spam) seemywebsite.com
wrote:



Jim Thompson wrote:
On Sun, 06 Jul 2008 11:42:09 -0700, John Larkin
jjlar... at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 06 Jul 2008 11:28:23 -0700, Jim Thompson
To-Email-Use-The-Envelope-I... at (no spam) My-Web-Site.com> wrote:

-- snip --

Pico-second speeds in CMOS are power hogs... my usual design
cross-over point is around 250-300MHz.

In a WiFi repeater chip I come from 5GHz down to 250MHz in CML, then
CMOS.

                                        ...Jim Thompson

Yes, but you went to school back when "circuit design" meant "circuit
design", not "simulating things you don't understand on software you
don't understand using a process you don't understand."

Yep.  I was educated 1958-1962 BC (before computers
                                                       |
Must have been a crap university - the University of Melbourne in
Australia had a computer on-site from 1956

http://en.wikipedia.org/wiki/CSIRAC

Michael A. Terrell wrote:

Are you sure it wasn't "Before Curmudgeons"? ;-)

I'm certified

On Sun, 6 Jul 2008 19:34:54 -0700 (PDT), bill.sloman at (no spam) ieee.org wrote:

On Jul 7, 5:39 am, Jim Thompson <To-Email-Use-The-Envelope-I... at (no spam) My-Web-
Site.com> wrote:
On Sun, 06 Jul 2008 12:27:26 -0700, Tim Wescott <t... at (no spam) seemywebsite.com
wrote:



Jim Thompson wrote:
On Sun, 06 Jul 2008 11:42:09 -0700, John Larkin
jjlar... at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 06 Jul 2008 11:28:23 -0700, Jim Thompson
To-Email-Use-The-Envelope-I... at (no spam) My-Web-Site.com> wrote:

-- snip --

Pico-second speeds in CMOS are power hogs... my usual design
cross-over point is around 250-300MHz.

In a WiFi repeater chip I come from 5GHz down to 250MHz in CML, then
CMOS.

                                        ...Jim Thompson

Yes, but you went to school back when "circuit design" meant "circuit
design", not "simulating things you don't understand on software you
don't understand using a process you don't understand."

Yep.  I was educated 1958-1962 BC (before computers
                                                       |
Must have been a crap university - the University of Melbourne in
Australia had a computer on-site from 1956

http://en.wikipedia.org/wiki/CSIRAC



I suppose that, for some people, being offensive is more important
than being right.

http://www.cedmagic.com/history/whirlwind-computer.html

http://en.wikipedia.org/wiki/Whirlwind_(computer)

John

bill.slo... at (no spam) ieee.org> wrote in message

news:a83c1ac6-b362-4459-b289-11756d6f22a6 at (no spam) t54g2000hsg.googlegroups.com...
"He doesn't ever seem to have designed stuff for a
living, though he does claim to have fixed complicated gear from time
to time, which isn't quite the same thing."

I seem to recall that many of his "fixes" ended up making his employer's
product more reliable over time than they were when the engineers first let
them loose.  That's the kind of guy who's worth even more than a regular old
design engineer...

On Mon, 07 Jul 2008 07:23:05 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon at (no spam) My-Web-Site.com> wrote:


On Sun, 06 Jul 2008 22:45:12 -0700, John Larkin
jjlarkin at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 06 Jul 2008 21:07:22 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon at (no spam) My-Web-Site.com> wrote:


On Sun, 06 Jul 2008 20:01:16 -0700, John Larkin
jjlarkin at (no spam) highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 6 Jul 2008 19:34:54 -0700 (PDT), bill.sloman at (no spam) ieee.org wrote:

On Jul 7, 5:39 am, Jim Thompson <To-Email-Use-The-Envelope-I... at (no spam) My-Web-
Site.com> wrote:
[snip]

Yep.  I was educated 1958-1962 BC (before computers
                                                       |
Must have been a crap university - the University of Melbourne in
Australia had a computer on-site from 1956

http://en.wikipedia.org/wiki/CSIRAC



I suppose that, for some people, being offensive is more important
than being right.

http://www.cedmagic.com/history/whirlwind-computer.html

http://en.wikipedia.org/wiki/Whirlwind_(computer)

John



Actually, I was exaggerating. The first IBM all-transistor mainframe
was in place at MIT before 1960, the year I took summer courses in FAP
and Fortran... and there was a tube version before that.

I also used a DEC PDP-8 to compose my thesis.

...Jim Thompson

Hey, I had a PDP-8 (my *own* PDP- when I was still an undergrad at
Tulane. 4K of 12-bit core and an ASR-33. I did control system
simulations for the turbine control systems on steamships, among other
amusements.

The PDP-8 was a horrible logic design, full of RC's and delay lines
and terrible stuff. The first PDP-11 wasn't a lot better; only the
later machines approached a proper disciplined, synchronous logic
design.

Tulane had a 704, or maybe it was a 7094, as the main campus computer.
All tubes, but hardware floating-point!

But nobody that I knew did circuit simulation in those days.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


Well, a few guys used an analog computer.


I did my first simulation around 1977, Berkeley Spice (modified to
correct Cbe), on some mainframe I can't quite remember now... does
7800 ring any bells?



Sounds like a VAX. Nice systems. I wish Windows was as stable as VMS.

My first circuit simulator was ECA, running on a PC/XT clone under
DOS. It was really quite good, with easy-to-specify nonlinear and
frequency-dependant parts and lots of fun tricks. And it would always
converge, and cruise right through divide-by-zero errors and keep
going.

John




' eca model of 50 mhz xtal oscillator
'
' JL 13 mar 92
'
' ECL OUTPUT IS NODE 10


' GENERATOR : USEFUL FOR TESTING

VGEN 0 0 .3
RGEN 1 0 .01

' CRYSTAL : Q == 30,000
' INITIAL LX CURRENT FORCES STARTUP

RX 10 5 30
CX 5 6 .0035P
LX 6 2 .00289489 , , I .002
CH 10 2 5P

' ADD A DUMMY RESISTOR TO AVOID OC ERROR...

R90 2 0 10K

' TANK CIRCUIT : Q == 50

C2 2 0 100P
C1 4 2 24.7P
L1 4 3 .47U
R2 3 0 3

' AMPLIFIER WITH ECL-LEVEL CLIPPING

V1 4 0 20 M 0.45
R1 9 0 1

' FOLLOW THAT WITH A 2.0 NSEC PROP DELAY

V2 9 0 1 D 2N
R8 10 0 10

Sounds like a VAX. Nice systems. I wish Windows was as stable as VMS.

Not in that era, could be a Burroughs or a CDC. I think that the VAXs
hit the 7000 series about 1983. VMS is stable, but it was designed
correctly in the first place.