Hi there,

I am using two 74LS90 ICs cascaded in series to divide down a clock
signal (f=1/60 Hz). A 74LS90 has a divide by 2 and a divide by 5
section in it. The 1min period clock pulse is therefore divided up
into:
2min, 5min, 10min and 25min periods.

the 2, 5 and 10min periods work OK, but the 25min doesn't. It turns
out to also be 10min rather than 25min.

My suspicion is that this problem is highlighted by the following
sentences in Motorola's datasheet:

"State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes."

I don't have a DSO to see if there are glitches on the divide by 5
output from the first 74LS90. (I just have an analog CRO), so I am
assuming there are glitches that are causing this problem.

I tried placing a single pole passive LPF in series from the div5
output to the CLK input of the 2nd 74LS90 to no avail. It seemed to
result in random periods coming from the outputs of the 2nd 74LS90.
I kept the resistor low enough (a few hundred ohms) so the input
current didn't stuff the logic levels up. And I tried capacitors of
0.1uF, 0.68uF and even 100uF (this 100uF stopped the lines from
toggling altogether !). All the set and preset pins on the 74LS90s
are tied low as required.

So is it possible to deglitch the output of a 74LS90 ?

regards
Peter

the 2, 5 and 10min periods work OK, but the 25min doesn't. It turns
out to also be 10min rather than 25min.

I don't have a DSO to see if there are glitches on the divide by 5
output from the first 74LS90. (I just have an analog CRO), so I am
assuming there are glitches that are causing this problem.

Hi there,

I am using two 74LS90 ICs cascaded in series to divide down a clock
signal (f=1/60 Hz). A 74LS90 has a divide by 2 and a divide by 5
section in it. The 1min period clock pulse is therefore divided up
into:
2min, 5min, 10min and 25min periods.

the 2, 5 and 10min periods work OK, but the 25min doesn't. It turns
out to also be 10min rather than 25min.

My suspicion is that this problem is highlighted by the following
sentences in Motorola's datasheet:

"State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes."

I don't have a DSO to see if there are glitches on the divide by 5
output from the first 74LS90. (I just have an analog CRO), so I am
assuming there are glitches that are causing this problem.

I tried placing a single pole passive LPF in series from the div5
output to the CLK input of the 2nd 74LS90 to no avail. It seemed to
result in random periods coming from the outputs of the 2nd 74LS90.
I kept the resistor low enough (a few hundred ohms) so the input
current didn't stuff the logic levels up. And I tried capacitors of
0.1uF, 0.68uF and even 100uF (this 100uF stopped the lines from
toggling altogether !). All the set and preset pins on the 74LS90s
are tied low as required.

So is it possible to deglitch the output of a 74LS90 ?

Hi there,

I am using two 74LS90 ICs cascaded in series to divide down a clock
signal (f=1/60 Hz). A 74LS90 has a divide by 2 and a divide by 5
section in it. The 1min period clock pulse is therefore divided up
into:
2min, 5min, 10min and 25min periods.

the 2, 5 and 10min periods work OK, but the 25min doesn't. It turns
out to also be 10min rather than 25min.

My suspicion is that this problem is highlighted by the following
sentences in Motorola's datasheet:

"State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes."

I am using two 74LS90 ICs cascaded in series to divide down a clock
signal (f=1/60 Hz). A 74LS90 has a divide by 2 and a divide by 5
section in it. The 1min period clock pulse is therefore divided up
into:
2min, 5min, 10min and 25min periods.

the 2, 5 and 10min periods work OK, but the 25min doesn't. It turns
out to also be 10min rather than 25min.

My suspicion is that this problem is highlighted by the following
sentences in Motorola's datasheet:

"State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes."

I don't have a DSO to see if there are glitches on the divide by 5
output from the first 74LS90. (I just have an analog CRO), so I am
assuming there are glitches that are causing this problem.

I tried placing a single pole passive LPF in series from the div5
output to the CLK input of the 2nd 74LS90 to no avail. It seemed to
result in random periods coming from the outputs of the 2nd 74LS90.
I kept the resistor low enough (a few hundred ohms) so the input
current didn't stuff the logic levels up. And I tried capacitors of
0.1uF, 0.68uF and even 100uF (this 100uF stopped the lines from
toggling altogether !). All the set and preset pins on the 74LS90s
are tied low as required.

So is it possible to deglitch the output of a 74LS90 ?

regards
Peter

Hi there,

I am using two 74LS90 ICs cascaded in series to divide down a clock
signal (f=1/60 Hz). A 74LS90 has a divide by 2 and a divide by 5
section in it. The 1min period clock pulse is therefore divided up
into:
2min, 5min, 10min and 25min periods.

the 2, 5 and 10min periods work OK, but the 25min doesn't. It turns
out to also be 10min rather than 25min.

I've seen exactly this problem on 7490 and 74LS90 when there was a stub of
more than 10cm (4") of wire attached to it's clock input - the signal
reflection in the wire triggered another clock pulse.

Arie de Muijnck

You're using some wrong counters. To make seconds from 60Hz, you'd better
use half a LS92 counter, followed by an LS90. You can use the circuit to
make minutes from seconds. Both types are ripple counters, so the outputs do
not change at the same time but they have no glitches. Glitches only occur
when you combine outputs with glue logic like gates. Maybe you can't trust
Gates anyway :)

petrus bitbyter

Hi there,

I am using two 74LS90 ICs cascaded in series to divide down a clock
signal (f=1/60 Hz). A 74LS90 has a divide by 2 and a divide by 5
section in it. The 1min period clock pulse is therefore divided up
into:
2min, 5min, 10min and 25min periods.

the 2, 5 and 10min periods work OK, but the 25min doesn't. It turns
out to also be 10min rather than 25min.

My suspicion is that this problem is highlighted by the following
sentences in Motorola's datasheet:

"State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes."

I don't have a DSO to see if there are glitches on the divide by 5
output from the first 74LS90. (I just have an analog CRO), so I am
assuming there are glitches that are causing this problem.

I tried placing a single pole passive LPF in series from the div5
output to the CLK input of the 2nd 74LS90 to no avail. It seemed to
result in random periods coming from the outputs of the 2nd 74LS90.
I kept the resistor low enough (a few hundred ohms) so the input
current didn't stuff the logic levels up. And I tried capacitors of
0.1uF, 0.68uF and even 100uF (this 100uF stopped the lines from
toggling altogether !). All the set and preset pins on the 74LS90s
are tied low as required.

So is it possible to deglitch the output of a 74LS90 ?

regards
Peter

So now I need to alleviate reflections causing the multiple triggers.
Do people have suggestions as to how I do that ?

Short cables ....

On Apr 26, 3:59 am, "Arie" <no.s...@nospam.com> wrote:
I've seen exactly this problem on 7490 and 74LS90 when there was a stub of
more than 10cm (4") of wire attached to it's clock input - the signal
reflection in the wire triggered another clock pulse.

Arie de Muijnck

Arie you are Correct !!!! I am exceedingly grateful that you
discovered my problem. Thank you. I had been trying to nut it out
for well over a week now.

I had wires of length 50-100cm coming off each Q output (routed via a
rotary switch to allow me to select whichever one I wanted to be fed
into the clk of a D flip flop in another part of the cct). Some Q
outputs were fed back into CLK input of the cascaded 74LS90 (and also
a 74LS92 which I didn't originally mention in an effort to simplify/
confine the problem).

Thank you also to John, Jeroen, Fred and cs_posting for taking an
interest and replying to my question, I appreciated all those
suggestions. For testing purposes I am easily able to speed up the clk
rates.

So now I need to alleviate reflections causing the multiple triggers.
Do people have suggestions as to how I do that ?

I've seen exactly this problem on 7490 and 74LS90 when there was a stub of
more than 10cm (4") of wire attached to it's clock input - the signal
reflection in the wire triggered another clock pulse.

Arie you are Correct !!!! I am exceedingly grateful that you
discovered my problem. Thank you. I had been trying to nut it out
for well over a week now.

I had wires of length 50-100cm coming off each Q output (routed via a
rotary switch to allow me to select whichever one I wanted to be fed
into the clk of a D flip flop in another part of the cct). Some Q
outputs were fed back into CLK input of the cascaded 74LS90 (and also
a 74LS92 which I didn't originally mention in an effort to simplify/
confine the problem).

So now I need to alleviate reflections causing the multiple triggers.
Do people have suggestions as to how I do that ?

Short cables ....

Short cables ....

Or, termination (series or parallel) of the long wires, at the far
ends, with a suitable resistance that will absorb the pulse and
prevent the reflection (or reduce its amplitude enough to avoid
false-triggering).

--
Dave Platt

On Apr 26, 3:59 am, "Arie" <no.s...@nospam.com> wrote:

I've seen exactly this problem on 7490 and 74LS90 when there was a stub of
more than 10cm (4") of wire attached to it's clock input - the signal
reflection in the wire triggered another clock pulse.

Arie de Muijnck

Arie you are Correct !!!! �I am exceedingly grateful that you
discovered my problem. �Thank you. �I had been trying to nut it out
for well over a week now.

I had wires of length 50-100cm coming off each Q output (routed via a
rotary switch to allow me to select whichever one I wanted to be fed
into the clk of a D flip flop in another part of the cct). Some Q
outputs were fed back into CLK input of the cascaded 74LS90 (and also
a 74LS92 which I didn't originally mention in an effort to simplify/
confine the problem).

Thank you also to John, Jeroen, Fred and cs_posting for taking an
interest and replying to my question, I appreciated all those
suggestions. For testing purposes I am easily able to speed up the clk
rates.

So now I need to alleviate reflections causing the multiple triggers.
Do people have suggestions as to how I do that ?

regards
Peter