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| Computers Forum Index » Computer Architecture - FPGA » WYSIWYG option in xilinx webpack 6.3 |
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| M.Randelzhofer |
 Posted: Mon Feb 21, 2005 2:00 am |
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Guest
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I used the wysiwyg option for a cpld design, and the compiler generates
wrong code. What's it's purpose ?
MIKE |
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| Jezwold |
| Posted: Mon Feb 21, 2005 8:00 am |
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Guest
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wysiwyg effects the place and route,or the logic asignment in the case
of a cpld and in this mode the logic is not minimised or refactored
which means that in most cases the logic is faster than a design which
has had a lot of reduction and refactoring performed.
The compiler producing 'wrong code' isnt effected by how much logic
optimisation is performed I suggest you look elsewhere for the cause of
your problems. |
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| M.Randelzhofer |
| Posted: Mon Feb 21, 2005 4:00 pm |
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Guest
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Quote: The compiler producing 'wrong code' isnt effected by how much logic
optimisation is performed I suggest you look elsewhere for the cause of
your problems.
Maybe i'm dreaming...
This is the VHDL code with the interesting 4bit counter ptc:
if (prc = 7) then
hf2 <= '0' ;
keyf2 <= '0' ;
ptc <= (others => '0') ;
if (ps2c_f = '1') then -- init hf2 during startbit
hf2 <= '1' ;
end if ;
else
if (ps2c_f = '1') then
ptc <= ptc + 1 ;
case ptc is
when "0001" | "0010" =>
if (sdat = '0') then
hf2 <= '0' ;
end if ;
when "0000" | "0011" | "0100" | "0101" | "0110" | "0111" =>
if (sdat = '1') then
hf2 <= '0' ;
end if ;
when "1000" =>
keyf2 <= hf2 ;
when others =>
end case ;
end if ;
end if ;
This translation is ok with not setting the wysiwyg flag:
FDCPE_ptc0 behaves exactly how it should.
FDCPE_ps2c_f: FDCPE port map (ps2c_f,ps2c_f_D,bsysclk,'0','0');
ps2c_f_D <= (NOT ed_ps2(0) AND ed_ps2(1));
FDCPE_ptc0: FDCPE port map (ptc(0),ptc_D(0),bsysclk,'0','0');
ptc_D(0) <= ((ptc(0) AND ps2c_f)
OR (NOT ptc(0) AND NOT ps2c_f)
OR (prc(0) AND prc(1) AND prc(2)));
FDCPE_ptc1: FDCPE port map (ptc(1),ptc_D(1),bsysclk,'0','0');
ptc_D(1) <= ((NOT ptc(0) AND NOT ptc(1))
OR (NOT ptc(1) AND NOT ps2c_f)
OR (ptc(0) AND ptc(1) AND ps2c_f)
OR (prc(0) AND prc(1) AND prc(2)));
FTCPE_ptc2: FTCPE port map (ptc(2),ptc_T(2),bsysclk,'0','0');
ptc_T(2) <= ((ptc(0) AND ptc(1) AND NOT prc(0) AND ps2c_f)
OR (ptc(0) AND ptc(1) AND NOT prc(1) AND ps2c_f)
OR (ptc(0) AND ptc(1) AND NOT prc(2) AND ps2c_f)
OR (ptc(2) AND prc(0) AND prc(1) AND prc(2)));
FTCPE_ptc3: FTCPE port map (ptc(3),ptc_T(3),bsysclk,'0','0');
ptc_T(3) <= ((prc(0) AND prc(1) AND ptc(3) AND prc(2))
OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(0) AND ps2c_f)
OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(1) AND ps2c_f)
OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(2) AND ps2c_f));
This output is wrong, with the wysiwyg flag enabled:
The FTCPE_ptc0 flipflop has a completely unrelated signal on it.
FDCPE_ps2c_f: FDCPE port map (ps2c_f,ps2c_f_D,bsysclk,'0','0');
ps2c_f_D <= (NOT ed_ps2(0) AND ed_ps2(1));
FTCPE_ptc0: FTCPE port map (ptc(0),iff1(4).EXP,bsysclk,'0','0');
FDCPE_ptc1: FDCPE port map (ptc(1),ptc_D(1),bsysclk,'0','0');
ptc_D(1) <= ((NOT ptc(1) AND NOT ptc(0))
OR (NOT ptc(1) AND NOT ps2c_f)
OR (ptc(1) AND ptc(0) AND ps2c_f)
OR (prc(2) AND prc(1) AND prc(0)));
FTCPE_ptc2: FTCPE port map (ptc(2),ptc_T(2),bsysclk,'0','0');
ptc_T(2) <= ((ptc(2) AND prc(2) AND prc(1) AND prc(0))
OR (ptc(1) AND NOT prc(2) AND ptc(0) AND ps2c_f)
OR (ptc(1) AND ptc(0) AND NOT prc(1) AND ps2c_f)
OR (ptc(1) AND ptc(0) AND NOT prc(0) AND ps2c_f));
FTCPE_ptc3: FTCPE port map (ptc(3),ptc_T(3),bsysclk,'0','0');
ptc_T(3) <= ((ptc(3) AND prc(2) AND prc(1) AND prc(0))
OR (ptc(2) AND ptc(1) AND NOT prc(2) AND ptc(0) AND ps2c_f)
OR (ptc(2) AND ptc(1) AND ptc(0) AND NOT prc(1) AND ps2c_f)
OR (ptc(2) AND ptc(1) AND ptc(0) AND NOT prc(0) AND ps2c_f));
Any hints ?
MIKE |
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| Newman |
| Posted: Tue Feb 22, 2005 4:00 am |
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Guest
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M.Randelzhofer wrote:
Quote: The compiler producing 'wrong code' isnt effected by how much logic
optimisation is performed I suggest you look elsewhere for the
cause of
your problems.
Maybe i'm dreaming...
This is the VHDL code with the interesting 4bit counter ptc:
if (prc = 7) then
hf2 <= '0' ;
keyf2 <= '0' ;
ptc <= (others => '0') ;
if (ps2c_f = '1') then -- init hf2 during startbit
hf2 <= '1' ;
end if ;
else
if (ps2c_f = '1') then
ptc <= ptc + 1 ;
case ptc is
when "0001" | "0010" =
if (sdat = '0') then
hf2 <= '0' ;
end if ;
when "0000" | "0011" | "0100" | "0101" | "0110" | "0111" =
if (sdat = '1') then
hf2 <= '0' ;
end if ;
when "1000" =
keyf2 <= hf2 ;
when others =
end case ;
end if ;
end if ;
This translation is ok with not setting the wysiwyg flag:
FDCPE_ptc0 behaves exactly how it should.
FDCPE_ps2c_f: FDCPE port map (ps2c_f,ps2c_f_D,bsysclk,'0','0');
ps2c_f_D <= (NOT ed_ps2(0) AND ed_ps2(1));
FDCPE_ptc0: FDCPE port map (ptc(0),ptc_D(0),bsysclk,'0','0');
ptc_D(0) <= ((ptc(0) AND ps2c_f)
OR (NOT ptc(0) AND NOT ps2c_f)
OR (prc(0) AND prc(1) AND prc(2)));
FDCPE_ptc1: FDCPE port map (ptc(1),ptc_D(1),bsysclk,'0','0');
ptc_D(1) <= ((NOT ptc(0) AND NOT ptc(1))
OR (NOT ptc(1) AND NOT ps2c_f)
OR (ptc(0) AND ptc(1) AND ps2c_f)
OR (prc(0) AND prc(1) AND prc(2)));
FTCPE_ptc2: FTCPE port map (ptc(2),ptc_T(2),bsysclk,'0','0');
ptc_T(2) <= ((ptc(0) AND ptc(1) AND NOT prc(0) AND ps2c_f)
OR (ptc(0) AND ptc(1) AND NOT prc(1) AND ps2c_f)
OR (ptc(0) AND ptc(1) AND NOT prc(2) AND ps2c_f)
OR (ptc(2) AND prc(0) AND prc(1) AND prc(2)));
FTCPE_ptc3: FTCPE port map (ptc(3),ptc_T(3),bsysclk,'0','0');
ptc_T(3) <= ((prc(0) AND prc(1) AND ptc(3) AND prc(2))
OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(0) AND ps2c_f)
OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(1) AND ps2c_f)
OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(2) AND ps2c_f));
This output is wrong, with the wysiwyg flag enabled:
The FTCPE_ptc0 flipflop has a completely unrelated signal on it.
FDCPE_ps2c_f: FDCPE port map (ps2c_f,ps2c_f_D,bsysclk,'0','0');
ps2c_f_D <= (NOT ed_ps2(0) AND ed_ps2(1));
FTCPE_ptc0: FTCPE port map (ptc(0),iff1(4).EXP,bsysclk,'0','0');
It's kind of hard to tell. I assume the unrelated signal you are
talking about is iff1(4).EXP. I do not see it in the exerpt, but it
might be an intermediate term that is generated in another macro-cell
that is a function of the HDL. Did you do a functional simulation of
the logic? Does the post synthesis design simulate as expected for
both the wysiwyg and non wysiwyg. Are there any synthesis warnings
concerning latches. Transparent latches are usually undesirable. Are
you getting logic failures in hardware that could be speed related,
cause I would guess that the wysiwyg could possible be slower.
Good-luck
-Newman
Quote:
FDCPE_ptc1: FDCPE port map (ptc(1),ptc_D(1),bsysclk,'0','0');
ptc_D(1) <= ((NOT ptc(1) AND NOT ptc(0))
OR (NOT ptc(1) AND NOT ps2c_f)
OR (ptc(1) AND ptc(0) AND ps2c_f)
OR (prc(2) AND prc(1) AND prc(0)));
FTCPE_ptc2: FTCPE port map (ptc(2),ptc_T(2),bsysclk,'0','0');
ptc_T(2) <= ((ptc(2) AND prc(2) AND prc(1) AND prc(0))
OR (ptc(1) AND NOT prc(2) AND ptc(0) AND ps2c_f)
OR (ptc(1) AND ptc(0) AND NOT prc(1) AND ps2c_f)
OR (ptc(1) AND ptc(0) AND NOT prc(0) AND ps2c_f));
FTCPE_ptc3: FTCPE port map (ptc(3),ptc_T(3),bsysclk,'0','0');
ptc_T(3) <= ((ptc(3) AND prc(2) AND prc(1) AND prc(0))
OR (ptc(2) AND ptc(1) AND NOT prc(2) AND ptc(0) AND ps2c_f)
OR (ptc(2) AND ptc(1) AND ptc(0) AND NOT prc(1) AND ps2c_f)
OR (ptc(2) AND ptc(1) AND ptc(0) AND NOT prc(0) AND ps2c_f));
Any hints ?
MIKE |
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