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| Computers Forum Index » Computer Languages (Forth) » Whatever happened to Eric LaForest?... |
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| Mux... |
 Posted: Fri Dec 04, 2009 5:29 am |
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Published a thesis a couple of years back on stack computers and what
not but has since (?) disappeared. Anyone know if he's still involved
with stack computers / forth?
-Mux |
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| Jecel... |
| Posted: Fri Dec 04, 2009 4:35 pm |
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On Dec 4, 3:29 am, Mux wrote:
Quote: Published a thesis a couple of years back on stack computers and what
not but has since (?) disappeared. Anyone know if he's still involved
with stack computers / forth?
He mentioned to me this April that he had been pushing the research
described in http://is.uwaterloo.ca/charles_laforest.html further and
got a ~200MHz Forth CPU running on an Altera Cyclone II FPGA, using
about 2 cycles per instruction on average.
He also described an interesting register/stack hybrid idea which
would be a MIPS-like processor where the first register would actually
be a data stack and the last register would be the PC counter and
return stack. He wasn't working on it anymore, however, and I last
heard from him in June.
-- Jecel |
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| Brad... |
| Posted: Thu Jan 21, 2010 7:49 pm |
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On Jan 21, 8:04 am, Eric <eric.lafor... at (no spam) gmail.com> wrote:
Quote: On Jan 19, 1:02 pm, rickman <gnu... at (no spam) gmail.com> wrote:
On Jan 19, 9:31 am, Eric <eric.lafor... at (no spam) gmail.com> wrote:
On Jan 10, 11:11 am, rickman <gnu... at (no spam) gmail.com> wrote:
I'm not trying to be absolutely "minimal" in terms of resources. Like
I said, I need a balance with an emphasis on minimizing instruction
memory. This is because I use smaller FPGAs in my designs. For
example, a current module has a Lattice part with six 9-kbit block
rams. This is also why I prefer to conserve that ninth bit if
practical.
Ah. So if I understand, you want a high instruction density since you
don't have much instruction memory available on-chip? Then yes, I can
see that 9th bit being valuable.
OTOH, if you want to run really big applications (or have large data
sets) you can execute from SPI flash. Big and cheap. The speed isn't
too bad if library code is kept on-chip. The SPI clock can be 60 to 80
MHz, and some chips have dual and quad modes. Then 8-bit is a
convenient instruction size.
-Brad |
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