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Message |
| gentel... |
 Posted: Tue Nov 03, 2009 6:15 am |
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Guest
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hello,all
i have built an edk project(based microblaze) . Because my
application c code is very big,when generating linker script ,i put some
big sections into the ddr and others into bram in microblaze.finally,it
displays the results through rs232.
for now,i want to try to import the EDK Project with microblaze as
Sub-system into a ISE project and i use the cammand h "export to project
navigator",then it generate a system.ise file.but,when i put the
.system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits)
files
into the board ,it does not work well.
however,if i replace the my_project.elf to TestApp_Memory.elf
(linking script in bram not ddr),it works well.
who can tell me the reasnon ? what can i should do?thank you very
much..
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| gentel... |
| Posted: Tue Nov 03, 2009 1:45 pm |
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Guest
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Quote: oh,i use the xilinx virtex_2 pro borad and it only has a cf card
interfa=
ce
.and i can not understand fully what you have said .now i do not know
how
to do=EF=BC=8Ccan you tell me some detailed steps or pdf
instructions?tha=
nks very
much.. =C2=A0 =C2=A0
if you have systemace based board then you can load the image from CF
also
it does use the JTAG debug interface for software loading, this
however only
works if you load from ace file, if you load the bit file over jtag
with debug cable
the soft would not get initialized
otherwise creating an custom ram loader is one ore more MAN-WEEK of
work
this is the time YOU have to spend doing real work, asking for help
doesnt
count as work done
Antti
thank you very much.thanks for your reply.
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