| Computers Forum Index » Computer Architecture - FPGA » Inter FPGA communication bus for Cypress Ez USB device... |
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| Test01... |
 Posted: Mon Nov 02, 2009 8:25 pm |
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Guest
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I design FPGA based test boards with CyPress EZ USB 2.0 Device. This
allows us to commmunicate to the test boards from the Host PC over
USB2.0 link from Host PC to the test board. The Ez USB device on the
test board connects to the FPGA with a simplified General Purpose
Interface.
But some times we have multipe FPGAs on the test board. We have a
mechanism to pass the primary General Purpose Bus from the EzUSB
device to the secondary General Purpose bus of the othe FPGAs.
I was curious if there is standard developed for inter FPGA
communication bus. It may be more efficient to follow such a
standard.
Any comments? |
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| LittleAlex... |
| Posted: Tue Nov 03, 2009 3:57 am |
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Guest
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On Nov 2, 12:25 pm, Test01 <cpan... at (no spam) yahoo.com> wrote:
Quote: I design FPGA based test boards with CyPress EZ USB 2.0 Device. This
allows us to commmunicate to the test boards from the Host PC over
USB2.0 link from Host PC to the test board. The Ez USB device on the
test board connects to the FPGA with a simplified General Purpose
Interface.
But some times we have multipe FPGAs on the test board. We have a
mechanism to pass the primary General Purpose Bus from the EzUSB
device to the secondary General Purpose bus of the othe FPGAs.
I was curious if there is standard developed for inter FPGA
communication bus. It may be more efficient to follow such a
standard.
Any comments?
In the early days of FPGAs, *nothing* got done in a single FPGA. One
board I worked on had 32 of them.
A google search gets 2.7 hits... Including papers from Altera and
MIT.
Your two basic options are "serial" and "parallel", and you can create
simplex, half-duplex and full-duplex interfaces.
I would be tempted to start with something that looked like a FIFO
inside the FPGA, and had data, clock and strobe on the interconnect
pins.
AL |
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