Hi all,
I am now using an Atmel AT45DB321D SPI flash booting xc5vsx50t-ff1136
and there is something wrong. First, the FPGA can be programmed
successfully, and the flash also can be programmed successfully both
directly & indirectly via iMPACT. But the FPGA just can't boot from
the flash. I checked the timing diagram of the signals: PROG_B,
INIT_B, M[2:0], FS[2:0], FCS_B, CCLK, MOSI, DIN, the MOSI did not
function right compared to the timing diagram in XAPP951 page8 (M[2:0]
=001,FS[2:0]=111). Pin MOSI clocks out 001100000.... after FCS_B goes
low and it should be 000010110...
I have no idea what's wrong and what should I do to fix this. So any
help would be thankfull!

Have you checked that your DONE signal has gone high thereby releasing
the chip out of config and into operation. Use the JTAG to do a status
read if you don't have access to the signal.

John Adair
Enterpoint Ltd. - Home of Merrick1. The ASIC Prototype Platform.

- Show quoted text -

On Oct 30, 1:57 am, John Adair <g... at (no spam) enterpoint.co.uk> wrote:

Have you checked that your DONE signal has gone high thereby releasing
the chip out of config and into operation. Use the JTAG to do a status
read if you don't have access to the signal.

John Adair
Enterpoint Ltd. - Home of Merrick1. The ASIC Prototype Platform.
- Show quoted text -

John,
Thank you for your reply. The signal DONE on my board drives a LED
through a
buffer. After FPGA successfully configured, the LED should light which
is not seen
when programming from flash. That's to say the FPGA is under
configuration all the
time.

Did you buffer the drive to the LED. If not this a common issue for
DONE not making the correct logic level. Double check with the JTAG
status to be sure.

John Adair
Enterpoint Ltd.

On 30 Oct, 01:29, crescent <hanpei... at (no spam) gmail.com> wrote:

On Oct 30, 1:57 am, John Adair <g... at (no spam) enterpoint.co.uk> wrote:

Have you checked that your DONE signal has gone high thereby releasing
the chip out of config and into operation. Use the JTAG to do a status
read if you don't have access to the signal.

John Adair
Enterpoint Ltd. - Home of Merrick1. The ASIC Prototype Platform.
- Show quoted text -

John,
Thank you for your reply. The signal DONE on my board drives a LED
through a
buffer. After FPGA successfully configured, the LED should light which
is not seen
when programming from flash. That's to say the FPGA is under
configuration all the
time.

On Oct 30, 7:38 am, John Adair <g... at (no spam) enterpoint.co.uk> wrote:





Did you buffer the drive to the LED. If not this a common issue for
DONE not making the correct logic level. Double check with the JTAG
status to be sure.

John Adair
Enterpoint Ltd.

On 30 Oct, 01:29, crescent <hanpei... at (no spam) gmail.com> wrote:

On Oct 30, 1:57 am, John Adair <g... at (no spam) enterpoint.co.uk> wrote:

Have you checked that your DONE signal has gone high thereby releasing
the chip out of config and into operation. Use the JTAG to do a status
read if you don't have access to the signal.

John Adair
Enterpoint Ltd. - Home of Merrick1. The ASIC Prototype Platform.
- Show quoted text -

John,
Thank you for your reply. The signal DONE on my board drives a LED
through a
buffer. After FPGA successfully configured, the LED should light which
is not seen
when programming from flash. That's to say the FPGA is under
configuration all the
time.

Other things to check:

1) Atmel Dataflash has a slightly different command set than
most SPI flash parts.  Be sure you have the right command
for continuous array read.

2) If you think it's a startup issue rather than loading, you
can enable the "internal Done pipe" in the bitgen options.

Regards,
Gabor- Hide quoted text -

- Show quoted text -