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| Computers Forum Index » Computer Architecture - FPGA » ISE 9.2 - RTL Schematic problem (separating of... |
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| sdaau... |
 Posted: Sat Oct 24, 2009 9:57 pm |
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Guest
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Hi all,
I am trying to experiment in ISE Webpack 9.2 on Linux, and I have a top
level VHDL file, which uses externally defined, or "included" components
(some in VHDL, some in Verilog).
I have a slight problem with RTL schematic view:
1) When I try to hook up these "included" components to pins defined for
the top level, all "included" components show up in RTL schematic view
(after the first "Push into Selected Instance") with their defined
schematic symbol - as they should.
2) However, if I then try to define signals, and use those to interconnect
the pins of the included components, the RTL schematic doesn't show the
top-level schematic symbols of the included components anymore - it shows
their constituents parts instead.
See the screenshot for reference:
http://img408.imageshack.us/img408/5024/isertlschematicmacroins.png
the image on left shows 1) - the image on right shows 2).
The way I'm trying to experiment is, by placing the individual components
in a top container, making some connections, and then viewing the 'one
below' top level RTL schematic - and then changing either the interfaces of
the components, or changing connections, until things seem right. Of
course, this concept will be possible only if I can display the included
objects with their schematic symbols (or "macros", as I understand they are
called??) .
Can anyone tell me why this happens, and possibly how to prevent it?
Thanks,
Cheers!
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| sdaau... |
| Posted: Sun Oct 25, 2009 12:05 am |
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Guest
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Hi all,
Quote:
2) However, if I then try to define signals, and use those to
interconnect
the pins of the included components, the RTL schematic doesn't show the
top-level schematic symbols of the included components anymore - it shows
their constituents parts instead.
Right, I think I got it - I stumbled accidentally across this document
which helped:
Xilinx XAPP918 Incremental Design Reuse with Partitions ... -
http://www.xilinx.com/support/documentation/application_notes/xapp918.pdf
Noobs may have noticed, that when you synthesize in ISE, and then view
Technology/RTL schematics, what you look at is .ngr/.ngc files. So what I
did is this:
- Compiled (that is, synthesized) my design with pins wired to individual
components so the RTL schematic shows.
- After it completes, right-click on all components that should "stay
together", and make them a new partition
- Synthesize again - one can notice that each element selected as a
partition, now has own .ngc/.ngr file
- Make all changes - i.e. use signals instead of pins - and synthesize
again; now the top schematic symbols of the instances will remain in view,
while the routing between them will change accordingly.
Cheers ! 
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