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| Computers Forum Index » Computer - DSP » Problems with DSP6713B ECLKOUT signal... |
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| liuhd_jeremy... |
 Posted: Wed Oct 21, 2009 5:12 pm |
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Guest
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I am developing a DSPC6713B board with one chip of CPLD. The Timer and
general purpose IO programs work normally. The input clock to the DSP CLKIN
pin is 25MHz and dsp works on the frequency of 200MHz.
When reset the DSP, the frequency of ECLKOUT,CLKOUT3, CLKOUT2 signal is
correct as the datasheet suggets. The frequency of ECLKOUT signal is CLKIN
divided by 2 and CLKOUT3,CLKOUT2 is divided by 8. Everything seems
perfect.
But SDRAM can't be written. A 32-bit SDRAM with 4 banks is connected to
the CE0.THE ECLKOUT signal is set to 80MHz(one fifth of 400MHz) ultilizing
the PLL intialization programs. BUT the ECLKOUT signal turns out to be very
strange. When Eclkout frequency is about 20MHz, the ECLKOUT signal wave is
a sinusoidal with the amplitude of about 3V, the minimum voltage of signal
is about 0.4V. As the ECLKOUT frequency increases to 50MHz, it is still a
sinusoidal wave, but the amplitude decreases to about 0.4V, the minimum
voltage is about 1.2V, that is, there exists more or less a 1.2v DC offset
in the ECLKOUT signal.
The dsp core supply voltage maintains at the level of 1.19V. It is the
same for the ECLKOUT signal if I seperated the DSP and SDRAM. BTW, the
signal is tested by a oscilloscope with bandwidth of 60MHz(200MSa/s). There
are no differences for the ECLKOUT signal with a different oscilloscope
with bandwidth of 100MHz(200MSa/s).
Any suggestion would be greated appreciated~~~~ |
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