Hi all,

I am simulating a entity with Modelsim (v6.5c). Modelsim
only displays the input/output signals of the simulated top entity.

When I run simulation Modelsim displays only changes of input/output
signals of the top entity verilog module i.e. testbench (in objects window
i.e. in wave window), but nothing happening with signals declared in the
instantiated verilog modules.
(PS: In Cadence SimVision, I know that I was able to see changes of all
signals in testbench and also in instantiated verilog modules, in wave
window)

Is there a way of viewing the internal signals declared in the instantiated
verilog modules in Modelsim in wave window?

Thanks very much

Regards

Thanks Nigel,

I was try that, but I'm still not able to see any changes of signals in
instantiated modules(in wave form window).

When I put some signals from instantiated verilog modules to wave form
window, after I hit "run" simulation those signals remain X.

Do you have any idea why is that so?

Best Regards      

---------------------------------------        
This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com

Is there a way of viewing the internal signals declared in the instantiated
verilog modules in Modelsim in wave window?

Hi all,

I am simulating a entity with Modelsim (v6.5c). Modelsim
only displays the input/output signals of the simulated top entity.

When I run simulation Modelsim displays only changes of input/output
signals of the top entity verilog module i.e. testbench (in objects window
i.e. in wave window), but nothing happening with signals declared in the
instantiated verilog modules.
(PS: In Cadence SimVision, I know that I was able to see changes of all
signals in testbench and also in instantiated verilog modules, in wave
window)

Is there a way of viewing the internal signals declared in the
instantiated
verilog modules in Modelsim in wave window?

Thanks very much

Regards

If you can see the signals you want in the Objects window and can add
them to the Wave window then you've sorted any optimization
accessibility issues.

The fact that you're seeing X on signals simply reflects the value
Modelsim has calculated for them.
You're into plain old circuit debug activity now !

As others have suggested, log all the signals in your design with
log -r /*
run the simulation and then back/forward trace signals to see where
the X is introduced.
The Dataflow window is very useful for this.

- Nigel

Hi,

When I said that I see X on signals... lets me explain you on example:
Suppose we have counter.v and counter_tb.v in our design. (counter_tb.v
instantiates counter.v)  
I add all signals from counter.v from objects window to wave window.
Then also add all signals from counter_tb.v objects window to wave window..
What I can see is all signal changes from counter_tb.v, including counter
instance signals from counter_tb.v.
With signals (in wave window) from counter.v nothing happening though
counter_tb.v instantiate counter.v module ????

Do you know how to see that signals in instantianed modules in wave
window.
(i.e. if we have clock signal in tesbench(counter_tb.v) which maps to clock
signal in counter.v
I can see clock signal from testbench toogling but nothing happens with
clock signal in counter.v (in wave window))

(PS: all mapping-signal orders etc... is just fine, just cant see what I
describe above)

Bets regards      

---------------------------------------        
This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com- Hide quoted text -

- Show quoted text -

If you can see the signals you want in the Objects window and can add
them to the Wave window then you've sorted any optimization
accessibility issues.

The fact that you're seeing X on signals simply reflects the value
Modelsim has calculated for them.
You're into plain old circuit debug activity now !

As others have suggested, log all the signals in your design with
log -r /*
run the simulation and then back/forward trace signals to see where
the X is introduced.
The Dataflow window is very useful for this.

- Nigel


Hi,