I'm trying to create a ring oscillator for my FPGA design but I've run
into some problems. Namely, it doesn't seem like any oscillation is
occurring. I've hooked up the output signal to LEDs and the serial port,
but neither of these shows any oscillations.

A few things I think might be happening is that the oscillation is so fast
I just can't see it, the oscillation is too fast for the board, it's
getting optimized out during synthesis, or (probably) my Verilog file is
implemented incorrectly.

Can you help me with this? See below for the Verilog modules I'm using.

module ringoscillator(
input wire stop,
output wire out
);

wire connector;
wire w1, w2, w3, w4;

nandgate inputGate(.i1(stop), .i2(connector), .out(w1));
invertergate inv1(.in(w1), .out(w2));
invertergate inv2(.in(w2), .out(w3));
invertergate inv3(.in(w3), .out(w4));
invertergate inv4(.in(w4), .out(connector));

assign out = connector;

endmodule

module nandgate(
input wire i1, i2,
output wire out);

assign out = ~(i1 & i2);
endmodule

module invertergate(
input wire in,
output wire out);

assign out = ~in;
endmodule

Thanks for any help!

I'm trying to create a ring oscillator for my FPGA design but I've run
into some problems. Namely, it doesn't seem like any oscillation is
occurring. I've hooked up the output signal to LEDs and the serial port,
but neither of these shows any oscillations.

A few things I think might be happening is that the oscillation is so fast
I just can't see it, the oscillation is too fast for the board, it's
getting optimized out during synthesis, or (probably) my Verilog file is
implemented incorrectly.

Can you help me with this? See below for the Verilog modules I'm using.

module ringoscillator(
input wire stop,
output wire out
);

wire connector;
wire w1, w2, w3, w4;

nandgate inputGate(.i1(stop), .i2(connector), .out(w1));
invertergate inv1(.in(w1), .out(w2));
invertergate inv2(.in(w2), .out(w3));
invertergate inv3(.in(w3), .out(w4));
invertergate inv4(.in(w4), .out(connector));

assign out = connector;

endmodule

module nandgate(
input wire i1, i2,
output wire out);

assign out = ~(i1 & i2);
endmodule

module invertergate(
input wire in,
output wire out);

assign out = ~in;
endmodule

Thanks for any help!

I'm trying to create a ring oscillator for my FPGA design but I've run
into some problems. Namely, it doesn't seem like any oscillation is
occurring. I've hooked up the output signal to LEDs and the serial port,
but neither of these shows any oscillations.

A few things I think might be happening is that the oscillation is so fast
I just can't see it, the oscillation is too fast for the board, it's
getting optimized out during synthesis, or (probably) my Verilog file is
implemented incorrectly.

[snip a ring oscillator]

Agreed, but the design I'm implementing is a Physically Unclonable
Function, which specifically calls for a ring oscillator.

-Sam Kerr



On Tue, 3 Nov 2009, Rob Gaddi wrote:
On Mon, 2 Nov 2009 09:20:45 -0500
Sam Kerr <stk... at (no spam) purdue.edu> wrote:

[snip a ring oscillator]

You know, for one pin, a tinylogic schmitt trigger, an R, and a C (sum
total < $0.10 in quantity), you could have a much easier to work with
clock source.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

"Sam Kerr" <stk... at (no spam) purdue.edu> wrote in message

news:alpine.WNT.2.00.0911020916180.1072 at (no spam) stkerr-Vista...

I'm trying to create a ring oscillator for my FPGA design but I've run
into some problems. Namely, it doesn't seem like any oscillation is
occurring. I've hooked up the output signal to LEDs and the serial port,
but neither of these shows any oscillations.

Here you might find useful reference design:

A. Maiti, R. Nagesh, A. Reddy, P. Schaumont, "Physical Unclonable Function
and True Random Number Generator: a Compact and Scalable Implementation,"
19th Great Lakes Symposium on VLSI (GLSVLSI 2009), May 2009.http://rijndael.ece.vt.edu/schaum/papers/2009glsvlsi.pdf



A few things I think might be happening is that the oscillation is so fast
I just can't see it, the oscillation is too fast for the board, it's
getting optimized out during synthesis, or (probably) my Verilog file is
implemented incorrectly.

Constraining inverter's output signals with 'KEEP' attribute will do the
job.
Also, the oscillation frequency for 3 INVs can reach 450-500MHz (when
implemented in V5).

Regards,
Krzysztof

"Antti" <antti.luk... at (no spam) googlemail.com> wrote in message

news:db41b833-0e92-421b-90d8-0ebc9f557571 at (no spam) j4g2000yqe.googlegroups.com...
On Nov 5, 8:41 pm, "Krzysztof Kepa" <nospam_blond... at (no spam) poczta.fm> wrote:

Also, the oscillation frequency for 3 INVs can reach 450-500MHz (when
implemented in V5).

I was able to measure ring oscillator frequency of 975MHz in V4
(but that signal would not travel long in V4 fabric)

Antti

Nice, was it on purpose?
I mean I'm just curious whether it required manual routing or simply 'just
happened' ?;)

Regards,
Krzysztof

On Mon, 2 Nov 2009 09:20:45 -0500
Sam Kerr <stkerr at (no spam) purdue.edu> wrote:

[snip a ring oscillator]

You know, for one pin, a tinylogic schmitt trigger, an R, and a C (sum
total < $0.10 in quantity), you could have a much easier to work with
clock source.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

I'm trying to create a ring oscillator for my FPGA design but I've run
into some problems. Namely, it doesn't seem like any oscillation is
occurring. I've hooked up the output signal to LEDs and the serial port,
but neither of these shows any oscillations.

A few things I think might be happening is that the oscillation is so fast
I just can't see it, the oscillation is too fast for the board, it's
getting optimized out during synthesis, or (probably) my Verilog file is
implemented incorrectly.

Also, the oscillation frequency for 3 INVs can reach 450-500MHz (when
implemented in V5).

I was able to measure ring oscillator frequency of 975MHz in V4
(but that signal would not travel long in V4 fabric)

Antti