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| Computers Forum Index » Computer Architecture - FPGA » Almost Full signal a clk before Wfull signal... |
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| RSGUPTA... |
 Posted: Sat Oct 31, 2009 12:53 pm |
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Guest
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Hello,
I am involved in a design where in i am using the asynchronous fifo
been given in the paper by sun-burst. (http://www.sunburst-design.com/
papers/CummingsSNUG2002SJ_FIFO2.pdf)
My only requirement in that design is that i need to make afull_n
signal asserted one clock before the wfull signal is asserted, but it
has been designed in such a way that both get triggerred at (no spam) the same
time.
It would be really thankfull to let me know what changes I need to do
in order to achieve this.
Regards, |
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| Jonathan Bromley... |
| Posted: Sat Oct 31, 2009 5:00 pm |
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Guest
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On Sat, 31 Oct 2009 05:53:04 -0700 (PDT), RSGUPTA wrote:
Quote: I am involved in a design where in i am using the asynchronous fifo
been given in the paper by sun-burst. (http://www.sunburst-design.com/
papers/CummingsSNUG2002SJ_FIFO2.pdf)
My only requirement in that design is that i need to make afull_n
signal asserted one clock before the wfull signal is asserted, but it
has been designed in such a way that both get triggerred at (no spam) the same
time.
Don't try to modify the asynch FIFO design unless you're
feeling exceptionally brave. Instead, add a one-place holding
buffer on the input side, in the input clock domain. Use the
FIFO in such a way that this holding buffer is normally unused.
Now, if the FIFO shows full, you can use that as an "almost full"
signal and drop the next input item into your holding buffer,
asserting "full" at the same time. As soon as the FIFO goes
non-full, transfer the holding buffer's data into the FIFO
(making it full once again) and, of course, deassert your
"full" status signal.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley at (no spam) MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated. |
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| Peter Alfke... |
| Posted: Sun Nov 01, 2009 6:07 am |
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Guest
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On Oct 31, 6:00 am, Jonathan Bromley <jonathan.brom... at (no spam) MYCOMPANY.com>
wrote:
Quote: On Sat, 31 Oct 2009 05:53:04 -0700 (PDT), RSGUPTA wrote:
I am involved in a design where in i am using the asynchronous fifo
been given in the paper by sun-burst. (http://www.sunburst-design.com/
papers/CummingsSNUG2002SJ_FIFO2.pdf)
My only requirement in that design is that i need to make afull_n
signal asserted one clock before the wfull signal is asserted, but it
has been designed in such a way that both get triggerred at (no spam) the same
time.
Don't try to modify the asynch FIFO design unless you're
feeling exceptionally brave. Instead, add a one-place holding
buffer on the input side, in the input clock domain. Use the
FIFO in such a way that this holding buffer is normally unused.
Now, if the FIFO shows full, you can use that as an "almost full"
signal and drop the next input item into your holding buffer,
asserting "full" at the same time. As soon as the FIFO goes
non-full, transfer the holding buffer's data into the FIFO
(making it full once again) and, of course, deassert your
"full" status signal.
--
Jonathan Bromley, Consultant
In asynchronous FIFOs, precision timing of both edges of Almost Full
is impossible.
AF is activated by a write operation, and is thus synchronous with the
write clock.
AF will later be deactivated by a read operation.
Since AF is usually viewed in the write clock domain, its deactivation
must be transferred from the read domain.
This inevitably causes issues with timing uncertainty and even
metastability.
The trailing edges of all the four status lines (Full, AF, Empty, AE)
are inherently "sloppy", since there is no defined phase relationship
between the two clocks. (Each status is activated by one clock domain,
and deactivated by the other).
Proper re-synchronization of the trailing edges causes an uncertainty
of several clock periods.
The leading edges can be very precise.
A more basic question is:
Why does the OP consider AF and F to be so critically important?
I usually view AF and F as emergency signals, indicating that the FIFO
is too small for the job at hand.
In general:
Asynchronous FIFOs have to straddle two clock domains.
They should not be burdened with unrealistic demands on the timing
precision of the trailing edges of their status signals.
Peter Alfke, still interested in FIFOs. |
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