Jon,
In the RTL there is not much you can do except add the signals to the
port list and bring them on up the hierarchy. Synthesis tools don't
support hierarchical references to nets. To do so they would have to
flatten the design hierarchy and it is not always wise to do that.
I usually just make a bus of all the signals in the child modules and
then route that up. If you use Xilinx's ChipScope insertion tool, then
this can do the work for you. The downside is that that tool is
terrible. In fact all the ChipScope tools are abysmal to use. I do
everything by hand and then only use the ChipScope analyzer tool. I
even name the signals by hand because the Xilinx tools are so bad. I
wish they would at least use a sane XML input format and document that
so we could just write scripts to feed the design information in. Even
better would be to publish the JTAG commands and let someone suck up
the information and stick it in a VCD file that could be read by your
favorite waveform viewer.
-Pete
On Oct 28, 6:36 am, "maxascent" <maxasc... at (no spam) yahoo.co.uk> wrote:
I have a design with some level of hierarchy and I want to connect a
chipscope ILA core to the bottom level.
For example say I have 3 modules A, B and C with a signal temp in C.
Module A is the top level with B inside A and C inside B.
I would of thought that I could just do the following
chipscope_ila U_ila(
.CLK (clk),
.CONTROL (control),
.TRIG0 (A.B.C.temp));
The ila is in the top level and I want to monitor temp.
When I try and synthesize it with Synplify the program just errors.
Can anyone tell me what I am ddoing wrong?
Thanks
Jon
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