Hi,

I inserted some circuit in source code for debug. These code aren't
ported as output and is monitored by chipscope. In order not to be
optimised by synplify, I use attribute syn_preserve to keep these
registers. But synplify still removed these signals, I can't insert
these signals into cdc file in ISE. Is there a way to keep these
signals so that it can be used in chipscope?

for example,

Hi,

I inserted some circuit in source code for debug. These code aren't
ported as output and is monitored by chipscope. In order not to be
optimised by synplify, I use attribute syn_preserve to keep these
registers. But synplify still removed these signals, I can't insert
these signals into cdc file in ISE. Is there a way to keep these signals
so that it can be used in chipscope?

for example,

On Tue, 27 Oct 2009 04:43:25 -0700, skyworld wrote:
Hi,

I inserted some circuit in source code for debug. These code aren't
ported as output and is monitored by chipscope. In order not to be
optimised by synplify, I use attribute syn_preserve to keep these
registers. But synplify still removed these signals, I can't insert
these signals into cdc file in ISE. Is there a way to keep these signals
so that it can be used in chipscope?

for example,

Rather then rely on syn_preserve I generally use a spare pin and then OR
all the signals that I want to protect together and connect the OR to the
pin.

skyworld,

The attribute to prevent objects to be removed away is syn_keep. In
your VHDL example, simply replace syn_preserve by syn_keep.

Note: syn_preserve has a bit of misleading name. This attribute
disables sequential optimizations on sequential elements. Such
optimizations include redundancy removal (removal of duplicate
registers). However, unused registers are still removed away even in
presence of syn_preserve.

Cheers,

- gael

skyworld wrote:
thanks for your reply. To my understanding, syn_keep is used to keep
wire signals and syn_preserve is used to keep sequential signals. The
signals I want to keep is generated in process(clk, reset)

Synthesis works from a device input pin to an output pin.
If my process(clk, reset) does not look at an input pin
*and* drive an output pin in the top entity,
I get no gates and no flops, in any case.

-- Mike Treseler

On 10月27日, 下�7时43分, skyworld <chenyong20... at (no spam) gmail.com> wrote:

Hi,

I inserted some circuit in source code for debug. These code aren't
ported as output and is monitored by chipscope. In order not to be
optimised by synplify, I use attribute syn_preserve to keep these
registers. But synplify still removed these signals, I can't insert
these signals into cdc file in ISE. Is there a way to keep these
signals so that it can be used in chipscope?

for example,

signal a : std_logic;
signal b : std_logic;
attribute syn_preserve : boolean;
attribute syn_preserve of a : signal is true;
attribute syn_preserve of b: signal is true;
process(clk, reset)
begin
a <= ...
b <= ...
end
signal a/b are internal signals and not sent to output port. how can I
keep these signals? thanks.

thanks for your reply. To my understanding, syn_keep is used to keep
wire signals and syn_preserve is used to keep sequential signals. The
signals I want to keep is generated in process(clk, reset)

I had a similar problem with chipscope cores.  Try using the syn_noprune
attribute which is an integer with a value of 1.  This worked for me where
syn-keep failed.

---Matthew Hicks



On 10月27日, 下�7时43分, skyworld <chenyong20... at (no spam) gmail.com> wrote:

Hi,

I inserted some circuit in source code for debug. These code aren't
ported as output and is monitored by chipscope. In order not to be
optimised by synplify, I use attribute syn_preserve to keep these
registers. But synplify still removed these signals, I can't insert
these signals into cdc file in ISE. Is there a way to keep these
signals so that it can be used in chipscope?

for example,

signal a : std_logic;
signal b : std_logic;
attribute syn_preserve : boolean;
attribute syn_preserve of a : signal is true;
attribute syn_preserve of b: signal is true;
process(clk, reset)
begin
a <= ...
b <= ...
end
signal a/b are internal signals and not sent to output port. how can I
keep these signals? thanks.- ��被引用文字 -

- 显示引用的文字 -

On 10月27日, 下�9时31分, General Schvantzkoph <schvantzk... at (no spam) yahoo.com
wrote:
On Tue, 27 Oct 2009 04:43:25 -0700, skyworld wrote:
Hi,

I inserted some circuit in source code for debug. These code aren't
ported as output and is monitored by chipscope. In order not to be
optimised by synplify, I use attribute syn_preserve to keep these
registers. But synplify still removed these signals, I can't insert
these signals into cdc file in ISE. Is there a way to keep these
signals so that it can be used in chipscope?

for example,

Rather then rely on syn_preserve I generally use a spare pin and then
OR all the signals that I want to protect together and connect the OR
to the pin.

Hi,

thanks for your reply. This is a big design and I don't have an option
to connect debug signals to a pin. That is the reason why I use
chipscope and use those annoying attributes.