Rudi,

Have you read

http://www.xilinx.com/support/documentation/user_guides/ug198.pdf

page 151, where they refer to the PIPE documents which details this
functionality?

On page 21 of the gen2 document from Intel, and the next pages.

http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf

The test equipment reporting a receiver present does a lot of work
(based on my reading of the Intel document), and there would be many
ways that in the FPGA you might not be performing the required
sequence per the standard.

Austin

Rudi,

I do not know.  That is the purpose of documentation, to document.

One thought I had is that this works by measuring the difference
between an open line, and a terminated line, at the transmitter.  Such
analog measurement techniques only work for an exact fixed length of
the PCIe bus connection.  If you are using extension cables, or an
extension card, the length of the transmission lines may affect the
measurement.

Austin

On Oct 27, 9:47 pm, austin <aus... at (no spam) xilinx.com> wrote:

Rudi,

I do not know.  That is the purpose of documentation, to document.

One thought I had is that this works by measuring the difference
between an open line, and a terminated line, at the transmitter.  Such
analog measurement techniques only work for an exact fixed length of
the PCIe bus connection.  If you are using extension cables, or an
extension card, the length of the transmission lines may affect the
measurement.

Austin

Hi Austin,

I feel that in this case the documentation fails to document.
The description for Receiver Detect is a) incomplete; and,
b) scattered throughout unrelated sections.

My understanding is that this logic works by measuring the
time it takes to charge the coupling capacitor. (It is present and
correct value on my board). Cable length should not matter.

Receiver Detection is described starting on page 151 in ug198.
It clearly shows a waveform diagram, where I enter powermode
2'b10, and the next cycle assert TXDETECTRX. And some time
later, I will get PHYSTATUS, that validates the value on RXSTATUS
lines.

But than, in table 5-14 (page 111) I find out that TXELECIDLE
also must be asserted to initiate Receiver Detection.

And again, in other parts of the document, I find that when
changing powermode, I need to wait for PHYSTATUS to indicate
that power mode has been changed (change completed).

I have tried the original description as on page 151, as well,
as adding the other bits I found out. And still, I consistently
get "No Receiver Detected".

The other side has no problem detecting my hardware.

Is there somebody who knows this stuff inside out and can
shed some light on how to make this work ?

Thanks,
rudi