I have a pcb with a Virtex 5 and a programmable clock generator. I want to
use an LVDS clcok signal from the clock gen to the fpga. The problem is
that the clock generators default output is two 3.3V signals. The fpga bank
is connected to 1.8V. I would like to know if this will be a problem having
a 3.3V signal going to a 1.8V bank. Once I have programmed the clock to be
LVDS output it should be ok but there is a brief period with the other
signals.

Thanks

Jon        

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