Hi,

I am trying to connect an IO signal from my microblaze to the external
top-level vhdl code without using xilinx GPIO IP.  My question is, couldn't
I make a port definition in the MHS file and connect to it? for example,

PORT Test_IO = Test_IO, DIR = I     // an external port not defined by gpio
ip

and then on my top-level VHDL I would connect to it in the port map by

Test_IO  => somesignal,

My second question is how can I read the signal value in microblaze.  With
xilinx's GPIO, I could read base address to get the value.  But now there's
no base address associated with Test_IO.

Best Regards

HV        

Hi,

I am trying to connect an IO signal from my microblaze to the external
top-level vhdl code without using xilinx GPIO IP. My question is,
couldn't
I make a port definition in the MHS file and connect to it? for example,

PORT Test_IO = Test_IO, DIR = I // an external port not defined by
gpio
ip

and then on my top-level VHDL I would connect to it in the port map by

Test_IO => somesignal,

My second question is how can I read the signal value in microblaze. With
xilinx's GPIO, I could read base address to get the value. But now
there's
no base address associated with Test_IO.

Best Regards

HV

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