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| Bernd Paysan... |
Posted: Sun Oct 25, 2009 2:31 am |
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Del Cecchi wrote:
Quote: You could use SOI, no bulk.
There still is a bulk, there is just no substrate, so the bulk is left
floating. The diodes I mentioned are sill there, supplying the bulk
when forward biased (this is the well-known effect of SOI to have
variable gate thresholds through charging and discharging the bulk below
the diodes threshold, unless you add in a real bulk contact like on
stock silicon wafers).
Quote: I don't get the point of the AC. Light bulbs and space heaters are AC
powered and still disipate power. What did I miss?
I can't tell you. Andy apparently doesn't care much about the physics
behind integrated circuits, his knowledge stops at the gate level. This
is completely ok for digital design, but I wonder why he makes that sort
of suggestions .
One interesting property of quantum mechanics is that for irreversible
logic, there's a minimum amount of energy that is necessary to make it
happen. Reversible logic does not have this drawback. Therefore,
people investigate into reversible logic, even though the actual
components to get that benefit are not in sigh (not even carbon nanotube
switches have these properties, even though they are much closer to the
physical limits for irreversible logic). Many people also forget that
quantum mechanics does not properly take changes in the system into
account, and that means that your reversible logic only works with the
predicted low power when the inputs are not changing any more - and this
is just the uninteresting case (the coherent one - changes in the system
lead to decoherence, and thereby to classical physics).
--
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/ |
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| Robert Myers... |
Posted: Sun Oct 25, 2009 2:32 am |
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On Oct 24, 9:59 pm, Robert Myers <rbmyers... at (no spam) gmail.com> wrote:
Quote: On Oct 24, 9:40 pm, Andrew Reilly <andrew-newsp... at (no spam) areilly.bpc-
users.org> wrote:
On Sat, 24 Oct 2009 12:25:40 -0700, Robert Myers wrote:
I don't have any insight into what being architecture-naive on the other
architectures might be, but, for Itanium, you have to start with deep
insight into the code in order to get a payback on all the fancy bells
and whistles. Itanium should be getting more instructions per clock,
not significantly fewer (that *was* the idea, wasn't it?).
I've not used an Itanium, but it would seem to have quite a bit of
practical similarity to the Texas Instruments TIC6000 series of VLIW DSP
processors, in that it is essentially in-order VLIW with predicated
instructions and some instruction encoding funkiness. That whole idea is
*predicated* on being able to software-pipeline loop bodies and do enough
iterations to make them a worthwhile fraction of your execution time.
From memory, Anton's TeX benchmark is the exact opposite: strictly
integer code of the twistiest non-loopy conditional nature. I would not
expect even a heroic compiler to get *any* significant parallel issues
going, at which point it falls back to being an in-order RISC-like
machine: not dramatically unlike a pre-Cortex ARM, or SPARC, as you said.
Now, Texas' compilers for the C6000 *are* heroic, and I've seen them
regularly schedule all eight possible instruction slots active per cycle,
for appropriate DSP code. The interesting thing is that this process is
*extremely* fragile. If the loop body contains too many instructions
(for whatever reason), or some other limitation, then the compiler seems
to throw up its hands and give you essentially single-instruction-per-
cycle code, which is (comparatively) hopeless. Smells like a box full of
heuristics, rather than reliable proof. The only way to proceed is to
hack the source code into little pieces and try variations until the
compiler behaves "well" again.
At least the TI parts *do* get low power consumption out of the deal, and
since they clock more slowly they don't have quite so many cycles to wait
for a cache miss. And no-one is trying to run TeX on them...
I get so tense here, trying to make sure I don't make a grotesque
mistake.
Your post made me chuckle. Thanks. I actually didn't even look at
the TeX numbers, only the ones I had first relied upon. As a seventh-
grade teacher remarked, my laziness might one day be my undoing.
Thanks for calling attention to the TI compiler. I've looked at the
TI DSP chips, but never gotten further.
You know just how heroic a heroic compiler really is. I don't know
whether David Dinucci (did I get it right?) is still following.
Forgive me for responding to my own post. It was right here, in this
forum, that Linus Tovalds, the one, the only, declared the stupidity
of software pipelinining because he was, well, you know, used to OoO
processors.
This is an amazing place. Kudos to Terje who straightened me out.
You can find him on David Kanter's forum, if you're still interested.
Robert. |
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| Andrew Reilly... |
Posted: Sun Oct 25, 2009 5:15 am |
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On Sat, 24 Oct 2009 12:25:40 -0700, Robert Myers wrote:
Quote: I don't have any insight into what being architecture-naive on the other
architectures might be, but, for Itanium, you have to start with deep
insight into the code in order to get a payback on all the fancy bells
and whistles. Itanium should be getting more instructions per clock,
not significantly fewer (that *was* the idea, wasn't it?).
I've not used an Itanium, but it would seem to have quite a bit of
practical similarity to the Texas Instruments TIC6000 series of VLIW DSP
processors, in that it is essentially in-order VLIW with predicated
instructions and some instruction encoding funkiness. That whole idea is
*predicated* on being able to software-pipeline loop bodies and do enough
iterations to make them a worthwhile fraction of your execution time.
From memory, Anton's TeX benchmark is the exact opposite: strictly
integer code of the twistiest non-loopy conditional nature. I would not
expect even a heroic compiler to get *any* significant parallel issues
going, at which point it falls back to being an in-order RISC-like
machine: not dramatically unlike a pre-Cortex ARM, or SPARC, as you said.
Now, Texas' compilers for the C6000 *are* heroic, and I've seen them
regularly schedule all eight possible instruction slots active per cycle,
for appropriate DSP code. The interesting thing is that this process is
*extremely* fragile. If the loop body contains too many instructions
(for whatever reason), or some other limitation, then the compiler seems
to throw up its hands and give you essentially single-instruction-per-
cycle code, which is (comparatively) hopeless. Smells like a box full of
heuristics, rather than reliable proof. The only way to proceed is to
hack the source code into little pieces and try variations until the
compiler behaves "well" again.
At least the TI parts *do* get low power consumption out of the deal, and
since they clock more slowly they don't have quite so many cycles to wait
for a cache miss. And no-one is trying to run TeX on them...
Cheers,
--
Andrew |
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| Andy \"Krazy\" Glew... |
Posted: Sun Oct 25, 2009 5:15 am |
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nmm1 at (no spam) cam.ac.uk wrote:
Quote: In article <4AE12FA9.1000706 at (no spam) patten-glew.net>,
Andy \"Krazy\" Glew <ag-news at (no spam) patten-glew.net> wrote:
Robert Myers wrote:
I am not aware of an Itanium shipped or proposed that had an "x86 core
on the side".
I am. I can't say how far the proposal got - it may never have got
beyond the back of the envelope stage, and then got flattened as a
project by management.
I am reasonably certain that you are misremembering or misunderstanding
a presentation that may have oversimplified things. |
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| Robert Myers... |
Posted: Sun Oct 25, 2009 8:32 pm |
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On Oct 25, 2:54 pm, Bernd Paysan <bernd.pay... at (no spam) gmx.de> wrote:
Quote: Robert Myers wrote:
Let's see. Quantum mechanics properly applied takes account of
everything in the whole universe, which is, so far as I know, quantum
mechanical and reversible in it's entirety.
Nope. That's just wishful thinking from people who do QM. The concepts
behind decoherence are partly understood, and some even quantified (e.g.
the critical temperature corresponds to what has been called "thermal
de-Broglie wavelength", which more or less describes the relation
between random changes in the conductor and a "volume of coherence"),
but overall, this is not part of QM. QM describes what happens within
the volume of coherence, classical physic describes what happens
outside. There is no accepted unified theory that gives a good reason
for this boundary and works equally well on both sides of the coherence
fence.
Note that when the "observer" is actually a quantum mechanical object,
it won't disturb the other parts of the system - it will be part of this
reversible dance.
Thanks. I understand the disconnect better. The problem of people
using different foundational language to describe quantum mechanics is
ancient.
I'm troubled by the idea that QM describes what happens inside some
coherence volume and classical physics happens elsewhere. If you take
an interesting limit of QM, you recover classical physics, an ancient
result that is reassuring to everyone, but "classical" systems still
obey the laws of QM. They just don't as readily display the weird
effects that make quantum mechanics *seem* so different from classical
physics.
Coherent radiation displays properties like speckle. For incoherent
radiation, the fundamental mathematics that lead to speckle are still
there, but they are blurred to the point where you can't see anything
that looks similarly interesting.
It's not as if, for light, there were some hard boundary: coherent and
incoherent. There are actually only degrees of coherency that can be
described without semantic sloppiness by the use of properly-
formulated correlation functions.
I've never been through a similar exercise with quantum mechanics, but
I'm fairly certain that the entire program would go through without
modification.
The problem is that, so far as I know, the mathematics of quantum
mechanics has no place for an "observer," which is always added as a
deus ex machina, and it is in trying to introduce an observer that
problems arise and mathematics and sometimes even sanity take a
beating.
Coherence theory is a *huge* improvement over talking about things
like "the collapse of the wavefunction," but I don't find the idea of
drawing a box and saying things are quantum mechanical within it and
"classical" outside it to be particularly helpful. I don't know how
to introduce the notion of an observer cleanly, but I don't think
anyone else does, either, even after the advent of coherence theory.
You can make the observer part of the wavefunction (or simply
recognize that, yes, indeed, the laboratory and the observer are part
of the wavefunction whether you want to think about it or not), but
then you are left with the problem of observing the observer.
Quote: Thus, even though you can't do operations with *no* net cost in
energy, we can still build and operate devices that act as quantum
mechanical computers to an arbitrarily good approximation.
No, we can't. The quantum computer people are struggling with the same
thermal de-Broglie wavelength as the superconducting people. Just that
in quantum computing, the wavelength also depends on how many bits your
system has - but unfortunately, it goes exponentially with the number of
bits. So you can either make it arbitrary slow for many bits, or reduce
the number of bits to an almost useless amount, but not both at the same
time.
When I say something like "you can build and operate" I am not meaning
to say what is practically possible (what can actually be done with
equipment that can at least be imagined with existing technology), but
rather to make a statement about what I believe the mathematics says.
I really have no clue as to how to build an actual device, and I'm
quite sure that there are important limitations that can be quantified
as in any other area of statistical physics, but I can't find anything
in the mathematics that would lead to the notion of QM in one place
and classical in another.
Robert. |
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Posted: Sun Oct 25, 2009 9:04 pm |
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In article <8v2dneGMDK_yJ3nXnZ2dnUVZ8oOdnZ2d at (no spam) lyse.net>,
Terje Mathisen <Terje.Mathisen at (no spam) tmsw.no> wrote:
Quote:
An in-order cpu requires the asm programmer and/or compiler writer to
figure out statically how long each of those chains will be, and then
unroll the code sufficiently to handle it. This btw. requires a _lot_
more architectural registers, and is quite brittle when faced with a new
cpu generation with slightly different latency numbers.
Well, yes, but it needs saying that that's not a REAL in-order CPU!
One of those finishes each instruction before starting the next.
Those are absolutely trivial to implement and program, and pretty
trivial to tune. They just tend to be a bit slow :-)
However, if one were to take the highly-threaded approach, as the
Tera MTA did, that's probably the right way to do it. At least to
start with.
Regards,
Nick Maclaren. |
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| Robert Myers... |
Posted: Sun Oct 25, 2009 9:47 pm |
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On Oct 25, 1:59 pm, "Andy \"Krazy\" Glew" <ag-n... at (no spam) patten-glew.net>
wrote:
Quote:
Over the years I have learned that, if at a dead end, one must ask
stupid questions and come up with blue sky ideas, questioning the
implicit assumptions of the field, and/or starting from first
principles. Apparently we are approaching such a dead end wrt
circuits. I'm not *that* afraid to embarrass myself. My definition of
a computer architect is the guy who is able to go in and call "Bullshit"
on any specialist in the team who is sandbagging and/or reporting
obstacles. I've simplified logic by 100x. Dave Papworth, my former
boss on P6, once showed that the process technology guys were
sandbagging by more than 30% - he asked me for my CRC Handbook of
Chemistry and Physics, looked up the physical properties of aluminum,
and went and banged heads together.
I've seen the most amazing things go by because no one would ask a
"stupid" question.
<snip>
Quote: I can't help but wonder if this is part of the problem: the search for
the perfect, the lowest possible power, as opposed to what can be done now.
Progress can't be made to order. Physics went through and has in many
ways recovered from a similar crisis of confidence. When I was
getting my BS, people were saying similar things: no more laboratory
scale experiments because we already knew too much (wrong), no more
data in important areas, like particle theory and astrophysics
(wrong). People do snicker about string theory, and they may have a
point, but that's just one aspect of a field that is flourishing in
areas that were once considered to be intellectual backwaters, like
the physics of the solid state.
The mispredictions were a matter of physics catching its breath. Too
much had happened too fast. I think that learning how to build and to
use computers effectively has been so successful that some period of
frustration was inevitable.
One prediction in physics was accurate: funding became quite scarce.
Robert. |
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| Robert Myers... |
Posted: Sun Oct 25, 2009 10:17 pm |
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On Oct 25, 3:12 pm, an... at (no spam) mips.complang.tuwien.ac.at (Anton Ertl)
wrote:
Quote:
Your theories of how binary translation works is interesting, because
Gforth 0.7.0 works like such a naive binary tranlator for
straight-line Forth code: It just concatenates the code fragments for
the VM instructions in the Forth code sequence together. However, for
VM control flow, Gforth uses indirect branches, and even naive binary
translators are more sophisticated. I also doubt that the
PA-RISC->IA64 binary translator is as naive as Gforth for
straight-line code.
I wasn't aware that I had offered a theory of binary translators, only
an observation about why Itanium seems an unattractive target
architecture for them.
There is one relatively modest idea that drives much of my interest in
this particular area. We all know that one of the easiest ways to
find out what a code does is to run it (with appropriate safeguards,
of course). Even the smallest clue from the output can serve as an
anchor to understanding even the most obscurely-written code.
Binary translators can simply translate, or they can try to be smart,
with varying degrees of success, by paying attention to what happens
when you actually run the code. It seems as promising an idea as OoO
hardware. The most promising place to optimize is close to the
action.
I don't know actually know of any circumstances, though, where any run-
time software approach yields significant benefits, other than for
languages like Java that *can't* run without run-time support. If I
knew of such an instance, that would be a good place to start thinking
about a theory of binary translators, but I don't know of any such
instances.
Robert. |
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| Anton Ertl... |
Posted: Sun Oct 25, 2009 11:12 pm |
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Robert Myers <rbmyersusa at (no spam) gmail.com> writes:
Quote: I don't have enough insight into the other architectures to comment.
I first looked at the chart and said, yup, just like I said, it's a
compiler built and tuned around x86.
Gcc? The first target was the 68k Architecture, so it's certainly not
built around IA32. Of course, different targets have received
different amounts of tuning, and IA32 is probably among those that
have received the most tuning.
But in any case, the performance advantage of IA32 implementations on
the Gforth benchmarks comes from indirect-branch prediction.
Quote: I just happened to have your charts fresh in mind when I made the
comment, and neither your results nor the fact that binary translation
doesn't work well is a surprise.
Your theories of how binary translation works is interesting, because
Gforth 0.7.0 works like such a naive binary tranlator for
straight-line Forth code: It just concatenates the code fragments for
the VM instructions in the Forth code sequence together. However, for
VM control flow, Gforth uses indirect branches, and even naive binary
translators are more sophisticated. I also doubt that the
PA-RISC->IA64 binary translator is as naive as Gforth for
straight-line code.
- anton
--
M. Anton Ertl Some things have to be seen to be believed
anton at (no spam) mips.complang.tuwien.ac.at Most things have to be believed to be seen
http://www.complang.tuwien.ac.at/anton/home.html |
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| Robert Myers... |
Posted: Mon Oct 26, 2009 12:07 am |
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On Oct 25, 6:05 pm, Bernd Paysan <bernd.pay... at (no spam) gmx.de> wrote:
Quote: Robert Myers wrote:
Coherence theory is a *huge* improvement over talking about things
like "the collapse of the wavefunction," but I don't find the idea of
drawing a box and saying things are quantum mechanical within it and
"classical" outside it to be particularly helpful.
It obviously is a very simplified view. Yes, there is no obvious and
"hard" boundary e.g. between coherent and incoherent light. It's just
to illustrate: the "classical physics" which we are used to, as it
describes human-scale effects, deals with incoherent light and matter.
QM deals with coherent light and matter. It's not so easy to say "just
put incoherent light into QM equations, and off you go with your
classical physics". QM tends to turn incoherent parts into coherent,
even when applied to larger scales (from Bose-Einstein condensate to
lasers), classical physic does the reverse.
That's why tropical storms and hurricanes are quantum mechanical?
They are chaotic in the small and highly organized in the large.
Collective modes arise in many different circumstances in physics.
The key step in most analyses has nothing to do with quantum
mechanics. You write down the governing equations, multiply by the
complex conjugate of a field variable, and take an appropriate
ensemble average. That's how it goes through in turbulence and
statistical optics, and, since the parabolic wave equation is exactly
Schrodinger's equation, the difference between doing it for a laser
beam and non-relativistic quantum mechanics would be one of applying
natural language labels to the field variables and potentials.
There are subtleties of statistical physics that are completely beyond
me that have to do with things like ergodicity and ensemble averages,
but the formal manipulations themselves should not be beyond a first-
year graduate student.
It may be that none of this has to do with the practical likelihood of
building a quantum computer or usable reversible logic. John
Bardeen's idea for the first transistor wasn't the basis of reliable
device, and Bardeen and his followers thought that the difficulty was
fundamental, but William Shockley showed otherwise. My major concern
is to be careful about absolute declarations based on a limited
understand of quantum mechanics. At this point, I don't know anyone
whose understanding is not limited.
Coherence theory is one powerful tool for making careful statements
where once there were vague and sweeping generalizations.
Robert. |
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| Terje Mathisen... |
Posted: Mon Oct 26, 2009 12:51 am |
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Robert Myers wrote:
Quote: On Oct 25, 4:10 am, Terje Mathisen<terje.wiig.mathi... at (no spam) gmail.com
I don't mind Kudos from you Robert, but I don't think I deserve it
this time:
I didn't post anything about Linus' OoO ideas.
Terje, you were kind enough to explain to me, in a private
correspondence, that, no matter how inept the coder or the compiler,
OoO hardware would eventually figure out and exploit a circumstance
where software pipelinging might conceivably have been helpful. That
is to say (not your words, but mine) OoO hardware knows how to do
software pipelining, even if, in some rare awkward instances, it might
take a while.
Right, this is exactly what a PPro and other OoO cpus was designed to
do: Figure out the dependency chains within and between each loop
iteration, and allow as many as possible to be in flight simultaneously,
so as to cover the chain latency.
An in-order cpu requires the asm programmer and/or compiler writer to
figure out statically how long each of those chains will be, and then
unroll the code sufficiently to handle it. This btw. requires a _lot_
more architectural registers, and is quite brittle when faced with a new
cpu generation with slightly different latency numbers.
Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching" |
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| Bernd Paysan... |
Posted: Mon Oct 26, 2009 1:26 am |
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Andy "Krazy" Glew wrote:
Quote: Och! Wounded I am, ad-hominem'ed. What did I ever do to you, Bernd?
Have you been taking lessons from Nick?
Seems to. Sorry for that.
Quote: However, what I am talking about - what I have picked up from
researchers in this field - is to still have power and ground rails at
(1.5V,0) - but to have signal rails that are at (+1.3,+0.7). Then
signal rails periodically reverse, to (+0.7,+1.3).
This is why, in my original post, I was careful to say `The
devices
will have to work within a range of changing voltages, say when "high"
is between k=1/3 and k=1 Vmax=(Vmean+k*Vswing), and "low" is between
k=1/3 and k=1 Vmin=(Vmean-k*Vswing).'
Where signal rails at (+0.7,+1.3) range, with power rails at
(+1.5,0), Vmean=1V, VSwing = 0.3V, Vmax=1.3V, Vmin=0.7V.
Can this be made to work? I'm sure that Bernd will tell me an answer;
and, if I am lucky, we may get an answer frm somebody with more
knowledge than either I or Bernd have. I think you can keep the
devices properly biased under such a scheme.
But then again, this is not my specialty.
Hm, separate bulk biasing changes the Vt (threshold voltage), so people
have been using it either to speed up the logic at cost of leakage, or
to reduce leakage at the cost of speed. By changing the bias voltage
depending on operating conditions, you can have speed up and power
saving when you need them. Reversing the "signal supply" however would
also require to negate the Vt (see bottom of posting), but then, you
could always pair up transistors (P+N, one of them will conduct). So
yes, maybe it can be made work.
Quote: Even if it can be made to work, is there any advantage to doing it?
The papers I know seem to be more on the theory side. The theoretical
advantage is obvious, it remains questionable if the current technology
allows practical advantage.
Quote: (It's interesting to think about why AC ultimately beat the DC systems
that Edison initially deployed. I don't think power efficiency in the
device was a big part; mainly it was the ability to transmit AC longer
distances, with the ease of transformers to change voltage level.
Dissipation in transmission was part of it. I don;t know if this has
any relevance to electronics.)
It has a bit - the problem space changed, and DC-DC converters are now
more efficient than AC-AC converters.
Quote: Over the years I have learned that, if at a dead end, one must ask
stupid questions and come up with blue sky ideas, questioning the
implicit assumptions of the field, and/or starting from first
principles. Apparently we are approaching such a dead end wrt
circuits. I'm not *that* afraid to embarrass myself. My definition
of a computer architect is the guy who is able to go in and call
"Bullshit" on any specialist in the team who is sandbagging and/or
reporting obstacles.
The solution to overcome these obstacles however is usually much more
difficult than simply calling "Bullshit" .
Quote: I can't help but wonder if this is part of the problem: the search for
the perfect, the lowest possible power, as opposed to what can be done
now.
In the lab, we are already close, as you point out below:
Quote: Anyway, this may be a moot point. IEEE Spectrum October 2000, p.40
has an article by Pushkar Apte & George Scalise at the SIA, mentioning
graphene base BiSFET (Bilayer pseudo-Spin Field Effect Transistors)
(not
to be confused with BISFET, the BI-Stable FET). They say the BiSFET
"needs only one-hundredth to one-thousandth the power of a standard
MOSFET".
BiSFETs also allow what I wanted above: change a "PMOS" (negative Vt) to
an "NMOS" (positive Vt) simply by changing a bias voltage. And with the
more ballistic movement of electrons in graphene or cabon nano-tube, the
fundamental requirements to make resonant, adiabatic reversible logic
are there - it remains to be seen if they can be implemented in large
scale, as well. The process steps are similar to what we do with
silicon: etch out parts, add insulation layers, make vias, and so on.
Just in the 1nm scale, not in the 45/32nm scale.
Sidenote about reversible computing: Often, people use a "history" to
make storing values in memory reversible. However, creating information
is just as costly as destroying it, so creating a history has no energy
benefit over replacing old information in a memory cell. The only
energy efficient reversible memory operation is to swap memory and
register values.
--
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/ |
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| Bernd Paysan... |
Posted: Mon Oct 26, 2009 2:05 am |
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Robert Myers wrote:
Quote: Coherence theory is a *huge* improvement over talking about things
like "the collapse of the wavefunction," but I don't find the idea of
drawing a box and saying things are quantum mechanical within it and
"classical" outside it to be particularly helpful.
It obviously is a very simplified view. Yes, there is no obvious and
"hard" boundary e.g. between coherent and incoherent light. It's just
to illustrate: the "classical physics" which we are used to, as it
describes human-scale effects, deals with incoherent light and matter.
QM deals with coherent light and matter. It's not so easy to say "just
put incoherent light into QM equations, and off you go with your
classical physics". QM tends to turn incoherent parts into coherent,
even when applied to larger scales (from Bose-Einstein condensate to
lasers), classical physic does the reverse. Coherence theory somehow
helps to understand how this works. There are still a lot of open
questions left.
--
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/ |
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| Del Cecchi... |
Posted: Mon Oct 26, 2009 2:53 am |
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"Bernd Paysan" <bernd.paysan at (no spam) gmx.de> wrote in message
news:nrbcr6-rs6.ln1 at (no spam) vimes.paysan.nom...
Quote: Del Cecchi wrote:
You could use SOI, no bulk. :-)
There still is a bulk, there is just no substrate, so the bulk is
left
floating. The diodes I mentioned are sill there, supplying the bulk
when forward biased (this is the well-known effect of SOI to have
variable gate thresholds through charging and discharging the bulk
below
the diodes threshold, unless you add in a real bulk contact like on
stock silicon wafers).
You could go fully depleted, although IBM didn't last I heard.
Quote:
I don't get the point of the AC. Light bulbs and space heaters are
AC
powered and still disipate power. What did I miss?
I can't tell you. Andy apparently doesn't care much about the
physics
behind integrated circuits, his knowledge stops at the gate level.
This
is completely ok for digital design, but I wonder why he makes that
sort
of suggestions  .
One interesting property of quantum mechanics is that for
irreversible
logic, there's a minimum amount of energy that is necessary to make
it
happen. Reversible logic does not have this drawback. Therefore,
people investigate into reversible logic, even though the actual
components to get that benefit are not in sigh (not even carbon
nanotube
switches have these properties, even though they are much closer to
the
physical limits for irreversible logic). Many people also forget
that
quantum mechanics does not properly take changes in the system into
account, and that means that your reversible logic only works with
the
predicted low power when the inputs are not changing any more - and
this
is just the uninteresting case (the coherent one - changes in the
system
lead to decoherence, and thereby to classical physics).
I am so disappointed. I thought QM explained everything.
The theory of circuits that require unobtanium to build is widespread.
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| Stephen Sprunk... |
Posted: Mon Oct 26, 2009 5:15 am |
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Guest
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Robert Myers wrote:
Quote: I don't know actually know of any circumstances, though, where any run-
time software approach yields significant benefits, other than for
languages like Java that *can't* run without run-time support. If I
knew of such an instance, that would be a good place to start thinking
about a theory of binary translators, but I don't know of any such
instances.
IIRC, HP's Dynamo, a run-time PA-RISC to PA-RISC binary translator, was
able to achieve a significant performance gain over just running the
binary natively. They also ported it to x86 under the name DynamoRIO,
though I can't recall the performance results.
DEC's binary translator (FX32?) made the Alpha, for a few months at
least, the fastest "x86" machine in existence.
MS's .NET stuff seems to run pretty fast, especially when you consider
all the safety checks that it always does which are usually left out of
native C/C++ binaries, garbage collection, etc. Some tests show that
it's actually _faster_ than native code, once you subtract the start-up
time hit.
Apple seems to be committed to their LLVM stuff, which is already
reaping huge graphics performance gains. Rosetta was pretty darn fast,
enough to be useful and transparent, though not quite as fast as native
code.
Run-time translation seems to have a lot of success stories; the
miserable failures of Transmeta and Intel may just be well-publicized
anomalies.
S
--
Stephen Sprunk "God does not play dice." --Albert Einstein
CCIE #3723 "God is an inveterate gambler, and He throws the
K5SSS dice at every possible opportunity." --Stephen Hawking |
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