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| jmariano... |
 Posted: Tue Oct 06, 2009 3:42 pm |
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Guest
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Dear Group,
I have very little experience in FPGA (and in digital design!).
As part of a research project I have to add to an existing microblaze
system, implemented on spartan 3 starter kit board, a pulse programmer
(PP). A PP is a system that outputs a given pattern to a set of
digital lines for a given time and then changes the pattern according
to a program.
There are several ways of implementing the PP but I have decided to
use what seams to me to be the simpler on: two blocks of RAM, say 2K
deep and 16 bits wide, pointed by the same address counter. One block
holds the time duration and the other the bit pattern. The control
block load's the contents of the first ram into a counter and latches
the content of the second one to the output. When the counter reaches
the end, the AC in incremented and the next time and pattern words are
loaded.
The IP access to RAM must be fast (this determines the time resolution
of the PP), but the access of the processor can be slow, since this is
done only once at the beginning of the experiment to write the
programming words and then the IP works by is one.
I was thinking on using BRAM to hold the data. Is this a good choice?
My other question is, what is the easiest way to implement microblaze
access the ram? I appreciate any commets on this.
I also appreciate if you could point me to somme examples or
application notes of a similar system (not a PP, but a system were
memory is accessed by an IP and microblaze), were I can get somme
ideas.
Tank you very much,
jmariano |
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| glen herrmannsfeldt... |
| Posted: Tue Oct 06, 2009 4:43 pm |
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jmariano <jmariano65 at (no spam) gmail.com> wrote:
< As part of a research project I have to add to an existing microblaze
< system, implemented on spartan 3 starter kit board, a pulse programmer
< (PP). A PP is a system that outputs a given pattern to a set of
< digital lines for a given time and then changes the pattern according
< to a program.
< There are several ways of implementing the PP but I have decided to
< use what seams to me to be the simpler on: two blocks of RAM, say 2K
< deep and 16 bits wide, pointed by the same address counter. One block
< holds the time duration and the other the bit pattern. The control
< block load's the contents of the first ram into a counter and latches
< the content of the second one to the output. When the counter reaches
< the end, the AC in incremented and the next time and pattern words are
< loaded.
< The IP access to RAM must be fast (this determines the time resolution
< of the PP), but the access of the processor can be slow, since this is
< done only once at the beginning of the experiment to write the
< programming words and then the IP works by is one.
There are tricks that can be used if RAM access isn't fast enough.
For one, you want to fetch the next value from RAM and have it ready
in a register as soon as the previous one is being clocked out.
That probably works as long as the count isn't too small (like one).
Otherwise it sounds fine.
By the way, if this is homework be sure to reference the newsgroup
as source for any ideas that you use.
-- glen |
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| backhus... |
| Posted: Wed Oct 07, 2009 6:10 am |
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Guest
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On 6 Okt., 17:42, jmariano <jmarian... at (no spam) gmail.com> wrote:
Quote: Dear Group,
I have very little experience in FPGA (and in digital design!).
As part of a research project I have to add to an existing microblaze
system, implemented on spartan 3 starter kit board, a pulse programmer
(PP). A PP is a system that outputs a given pattern to a set of
digital lines for a given time and then changes the pattern according
to a program.
There are several ways of implementing the PP but I have decided to
use what seams to me to be the simpler on: two blocks of RAM, say 2K
deep and 16 bits wide, pointed by the same address counter. One block
holds the time duration and the other the bit pattern. The control
block load's the contents of the first ram into a counter and latches
the content of the second one to the output. When the counter reaches
the end, the AC in incremented and the next time and pattern words are
loaded.
The IP access to RAM must be fast (this determines the time resolution
of the PP), but the access of the processor can be slow, since this is
done only once at the beginning of the experiment to write the
programming words and then the IP works by is one.
I was thinking on using BRAM to hold the data. Is this a good choice?
My other question is, what is the easiest way to implement microblaze
access the ram? I appreciate any commets on this.
I also appreciate if you could point me to somme examples or
application notes of a similar system (not a PP, but a system were
memory is accessed by an IP and microblaze), were I can get somme
ideas.
Tank you very much,
jmariano
Hi,
if the processor is just needed for loading the RAM, a MicroBlaze may
be oversized for such a small task.
Picoblaze would be sufficient. And it comes with a UART, if you want
to use that kind of interface.
If you are going to use more complex intefaces like LAN a Microblaze
would be a better choice, of course.
For the microblaze there's a SRAM interface core available. It's
intended to acess register banks of peripheral devices, and sometimes
used to connect to the LAN interface chips on the development boards.
But that's just what you need, because your PP is just some interface
with a large register set (2K).
Remember, that you have to calculate BRAM ressources. MB needs some
BRAMS for Cache etc.. Or you might implement the core without cache.
You probably don't need that much performance.
Have a nice synthesis
Eilert |
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| -jg... |
| Posted: Wed Oct 07, 2009 8:22 am |
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On Oct 7, 4:42 am, jmariano <jmarian... at (no spam) gmail.com> wrote:
Quote:
The IP access to RAM must be fast (this determines the time resolution
of the PP),
Not quite. If you load pulse counters, for example, the RAM sets the
reload time, but the time-resolution can be smaller than the ram
access. Ram access sets the pulse update rates.
You could also use a simple scheme like run length coding, to expand
(compress?) what the ram holds, relative to the pulse resolution.
With a FPGA, you have a LOT of design freedom :)
-jg |
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| Paul Pham... |
| Posted: Wed Oct 28, 2009 9:01 am |
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Hi jmariano,
I have implemented a similar FPGA-based pulse programmer system for my
master's thesis, but instead of a Microblaze, I ended up designing a
custom processor and instruction set architecture just for outputting
pulses, detecting input pulses, looping, executing subroutines, and
branching conditionally. The problem with using a general-purpose
processor is that precise timing of the output cannot be guaranteed,
so I assume you are just using the Microblaze to load your banks of
SRAM before letting the timer run and stream the pulses directly from
memory.
There appear to be several Microblaze modules available on
http://www.opencores.org, maybe you can adapt some of them to your
needs.
All of my project's design documents are released as open source on
SourceForge. Perhaps the VHDL source code will give you some ideas,
although the board I used is a custom design (also released on the
website).
http://pulse-sequencer.svn.sourceforge.net/viewvc/pulse-sequencer/firmware/sequencer-vhdl/
I assume you are designing this pulse programmer for scientific
applications, and if so, I would like to hear about it by personal e-
mail.
Good luck,
Paul
On Oct 6, 8:42 am, jmariano <jmarian... at (no spam) gmail.com> wrote:
Quote: Dear Group,
I have very little experience in FPGA (and in digital design!).
As part of a research project I have to add to an existing microblaze
system, implemented on spartan 3 starter kit board, apulseprogrammer
(PP). A PP is a system that outputs a given pattern to a set of
digital lines for a given time and then changes the pattern according
to a program.
Quote: There are several ways of implementing the PP but I have decided to
use what seams to me to be the simpler on: two blocks of RAM, say 2K
deep and 16 bits wide, pointed by the same address counter. One block
holds the time duration and the other the bit pattern. The control
block load's the contents of the first ram into a counter and latches
the content of the second one to the output. When the counter reaches
the end, the AC in incremented and the next time and pattern words are
loaded.
The IP access to RAM must be fast (this determines the time resolution
of the PP), but the access of the processor can be slow, since this is
done only once at the beginning of the experiment to write the
programming words and then the IP works by is one.
I was thinking on using BRAM to hold the data. Is this a good choice?
My other question is, what is the easiest way to implement microblaze
access the ram? I appreciate any commets on this.
I also appreciate if you could point me to somme examples or
application notes of a similar system (not a PP, but a system were
memory is accessed by an IP and microblaze), were I can get somme
ideas.
Tank you very much,
jmariano |
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