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| Computers Forum Index » Computer - Cadence » Finding Missing layout pins... |
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Message |
| PolyPusher... |
 Posted: Mon Sep 14, 2009 4:21 pm |
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Guest
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I have a master that is LVS clean with Calibre, but one of the pins is
not being recognized by layout XL(It appears to be the case). When
this master(cell) is used in the next level of heirarchy, the issue
outlined below happens...
schematic has:
geGetSelectedSet(cvSch)~>instTerms~>net~>name
(("vbatt" "gnd" "hrx"))
Where the mapping from the instance to these names are
Instance:Cellname:instTerms - Signal
"I293:pad_boac_66x80:io - hrx"
"I293:pad_boac_66x80:vdd - vbatt"
"I293:pad_boac_66x80:vss - gnd"
After bringing this pad_boac_66x80 cell into the database(next level
of heirarchy) the io instTerm
is missing in layout and the mapping looks like this.
geGetSelectedSet(cvLay)~>instTerms~>net~>name
(("vbatt" "gnd"))
Mapping ends up being.....
Instance:Cellname:instTerms - Signal
"I293:pad_boac_66x80:vdd - vbatt"
"I293:pad_boac_66x80:vss - gnd"
.....which obviously breaks the connectivity.
I want to ride some Skill code to find this issue in layout, but
cannot find any info on the missing pin, broken connectivity. Is
this possible and if so does anyone have any ideas how to do this?
Thank you in advance for any help,
PolyPusher  |
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