| Computers Forum Index » Computer - CAD - Synthetis » [Chip-Level synthesis] I/O synthesis constraints |
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| Guest |
 Posted: Wed Dec 19, 2007 6:03 am |
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Hi all,
What's the methodology for the chip-level synthesis?
I need to apply timing constraints to the Top level of the Chip [the
hierarchical level, which is next to the I/O's].
So, how should I do so? Actually I have all the constraints on the
I'O's [defined by SPEC]. So, how should I translate the constraints in
order to apply them on the Top level [the highest hierarchy just next
to the I/O ring hierarchy]?
Please help. |
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